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| Patent # | Description |
|---|---|
| US-6,799,278 |
System and method for processing power management signals in a peer bus
architecture A system and method for handling number power management signals, such as PME# signals, is disclosed. The power management signal lines are coupled to general... |
| US-6,799,277 |
System and method for monitoring software Systems and methods for monitoring, testing, distribution, and use of computer software with associated methods and systems for repeatedly contacting a software... |
| US-6,799,276 |
Method and apparatus for restraining connection request stream associated
with high volume burst client in a... According to the present invention, method, apparatus, and computer readable medium for restraining a connection request stream from a burst client are... |
| US-6,799,275 |
Method and apparatus for securing a secure processor A method and apparatus for securing a secure processor is described. A plurality of spurious points are added to a biometric template. A received biometric data... |
| US-6,799,274 |
Device comprising encryption circuitry enabled by comparing an operating
spectral signature to an initial... A device is disclosed comprising encryption circuitry for encrypting plaintext data into ciphertext data. A memory stores an initial spectral signature... |
| US-6,799,273 |
Data processing system and method for mutual identification between
apparatuses A storage unit in a first mutual identification unit stores master key data and a second storage unit in a second mutual identification unit stores ... |
| US-6,799,272 |
Remote device authentication system Method and system for authenticating a remote device are disclosed by an arrangement in which the remote device and an authentication center each contain an... |
| US-6,799,271 |
Method and system for authenticating user and providing service A service providing method which uses a user terminal, a service providing apparatus, and an authentication apparatus is disclosed. In the method, authentication... |
| US-6,799,270 |
System and method for secure distribution of digital information to a chain
of computer system nodes in a network Described are a system and method for securely distributing session keys over a network to each node in a chain of computer system nodes. The chain of nodes... |
| US-6,799,269 |
Virtual shadow registers and virtual register windows A direct memory access and direct register access (DMA/DRA) controller and method are used on microprocessors, microcontrollers and digital signal processors... |
| US-6,799,268 |
Branch ordering buffer A branch ordering buffer. One disclosed apparatus includes a processor state management circuit to maintain a primary state and a shadow state, each of the... |
| US-6,799,267 |
Packet processor A packet processor having a general-purpose arithmetic operator and another dedicated circuit, which extracts a particular field from the general-purpose... |
| US-6,799,266 |
Methods and apparatus for reducing the size of code with an exposed
pipeline by encoding NOP operations as... A method for reducing total code size in a processor having an exposed pipeline may include the steps of determining a latency between a load instruction, and a... |
| US-6,799,265 |
Dependency checking for reconfigurable logic A data dependency checking table is used with a reconfigurable chip. A control processing chip on the reconfigurable chip can load variable size blocks of data... |
| US-6,799,264 |
Memory accelerator for ARM processor pre-fetching multiple instructions
from cyclically sequential memory... A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically... |
| US-6,799,263 |
Prefetch instruction for an unpredicted path including a flush field for
indicating whether earlier prefetches... A method for prefetching instructions into cache memory using a prefetch instruction. The prefetch instruction contains a target field, a count field, a cache... |
| US-6,799,262 |
Apparatus and method for creating instruction groups for explicity parallel
architectures An apparatus and method for creating instruction groups for explicitly parallel architectures is provided. The apparatus and method gather information about the... |
| US-6,799,261 |
Memory interface with fractional addressing A memory interface device (100) providing a fractional address interface between a data processor (104) and a memory system (102) and a method for retrieving... |
| US-6,799,260 |
Dynamic storage management Apparatus and methods for managing storage. A storage system may receive a request from a host, for example, to allocate n blocks of storage. The storage system... |
| US-6,799,259 |
Security system for data processing applications A system for dynamically controlling activation status of multiple data storage structures in a single computer so that a single computer can be dynamically... |
| US-6,799,258 |
Methods and apparatus for point-in-time volumes Methods and apparatus for point-in-time volumes are provided. A relationship is enabled between a source volume and point-in-time volume. Copying a data chunk to... |
| US-6,799,257 |
Method and apparatus to control memory accesses A method and apparatus for accessing memory comprising monitoring memory accesses from a hardware prefetcher and determining whether the memory accesses from the... |
| US-6,799,256 |
System and method for multi-bit flash reads using dual dynamic references A system and methodology is provided for proper reading of multi-bit memory cells in a memory device. A first reference cell and a second reference cell is... |
| US-6,799,255 |
Storage mapping and partitioning among multiple host processors A storage controller for controling access to data storage has a memory and at least one data port for a data network including host processors. The memory is... |
| US-6,799,254 |
Memory manager for a common memory The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this ... |
| US-6,799,253 |
Stochastic scratchpad storage management technique Methods and apparatus for dynamically allocating space within virtual memory at run-time while substantially minimizing an associated path length are disclosed.... |
| US-6,799,252 |
High-performance modular memory system with crossbar connections A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that... |
| US-6,799,251 |
Performance-based caching A method and system are provided for caching data in a manner that substantially maintains a desired level of system performance. A cache server receives data... |
| US-6,799,250 |
Cache control device A cache control device of the invention comprises a first register for holding address data, a second register for holding address data held by the first... |
| US-6,799,249 |
Split control for IP read and write cache misses An apparatus for and method of queuing memory access requests resulting from level two cache memory misses. The requests are preferably queued separately by... |
| US-6,799,248 |
Cache management system for a network data node having a cache memory
manager for selectively using different... A network accelerator storage caching system manages a number of cache management systems and may be inserted at any point in a network to provide a... |
| US-6,799,247 |
Remote memory processor architecture A remote memory processor architecture which provides an embedded processor with access to a large off-chip memory space via a HOST processor bus. An on-chip... |
| US-6,799,246 |
Memory interface for reading/writing data from/to a memory A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of... |
| US-6,799,245 |
Raid apparatus storing a plurality of some logical volumes on different
disk units A RAID apparatus includes having a plurality of same logical volumes allocated on a real volume. The real volume is so designed that a plurality of same logical... |
| US-6,799,244 |
Storage control unit with a volatile cache and a non-volatile backup cache
for processing read and write requests A subsystem and a subsystem processing method are disclosed in which a storage control unit 2000 interposed between a plurality of disk units 3000 and a host... |
| US-6,799,243 |
Method and apparatus for detecting a match in an intra-row configurable cam
system A method and apparatus for detecting a match in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and match flag... |
| US-6,799,242 |
Optical disc player with sleep mode An optical disc player enters a sleep (low power consumption) mode when inactive for a predetermined time. The optical disc player includes a buffer RAM for... |
| US-6,799,241 |
Method for dynamically adjusting a memory page closing policy A method for dynamically adjusting a memory page-closing policy for computer systems employing various types of DRAM memory partitioned into one or more memory... |
| US-6,799,240 |
SRAM bus architecture and interconnect to an FPGA An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the... |
| US-6,799,239 |
Centrally distributed serial bus A bus for a computer system receives serial data from each subsystem and simultaneously broadcasts the data to all subsystems. The computer system includes bus... |
| US-6,799,238 |
Bus speed controller using switches Switches are used to serially isolate connectors for peripheral devices on a bus. Bus speed is selected based on the number of peripheral devices coupled to the... |
| US-6,799,237 |
Identifying and synchronizing incompatibilities between a portable computer
and a docking station The present invention comprises a system and method for insuring that a notebook computer and a docking station are compatible. This determination is made by... |
| US-6,799,236 |
Methods and apparatus for executing code while avoiding interference Mechanisms and techniques operate in a computerized device to execute critical code without interference from interruptions. Critical code is registered for... |
| US-6,799,235 |
Daisy chain latency reduction Transmitting data on a serial data transmission path to reduce latency including reading only enough of a device address of a serial data word to determine if... |
| US-6,799,234 |
Apparatus and method for randomly assigning slots in a PCI backplane A system and method for automatically assigning resources to a slave device inserted into a PCI backplane utilizes pairs of PCI GNT/REQ lines as bus lines of a... |
| US-6,799,233 |
Generalized I2C slave transmitter/receiver state machine A robust state machine is provided for controlling a slave interface to an I.sup.2 C-bus. The state machine is configured to enforce the slave-device-protocol of... |
| US-6,799,232 |
Automatic byte swap and alignment for descriptor-based direct memory access
data transfers A physical interface card for connection to a data bus associated with a data network node is provided. The physical interface card is adapted to perform without... |
| US-6,799,231 |
Virtual I/O device coupled to memory controller The invention relates to a virtual I/O device coupled to a memory controller in a microprocessor of computer, the virtual I/O device and a memory unit being in... |
| US-6,799,230 |
Peripheral device exchanging data with one of higher-order devices by
switching interfaces A control unit of a peripheral device enables data to be exchanged between a unit of the peripheral device and one of a plurality of higher-order devices by... |
| US-6,799,229 |
Data-burst-count-base receive FIFO control design and early packet discard
for DMA optimization A system which includes a DMA (Direct Memory Access) interface and a MAC (Media Access Control) interface. A data FIFO and data burst information FIFO are... |
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