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| Patent # | Description |
|---|---|
| US-6,900,700 |
Communication semiconductor integrated circuit and radio communication
system A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip... |
| US-6,900,699 |
Phase synchronous multiple LC tank oscillator A phase synchronous multiple LC tank oscillator includes a plurality of oscillator stages configured to oscillate synchronously. The phase of each of the... |
| US-6,900,698 |
Negative feedback amplifier with electrostatic discharge protection circuit A negative feedback amplifier which alleviates reduction in band width and effectively protects an amplifier from electrostatic discharge (ESD). A node is... |
| US-6,900,697 |
Method and system for providing power management in a radio frequency power
amplifier by dynamically adjusting... A method for providing power management in a radio frequency power amplifier is provided. An input voltage is received. A digital power supply signal is... |
| US-6,900,696 |
Shared-current electronic systems Shared-current electronic systems (10, 20, 26, 30, 38, 48, 66, 70, 82, 90, 96, 100, 104, 108, 118, and 122) include two or more solid-state electronic devices,... |
| US-6,900,695 |
Reconfigurable broadband active power splitter ditto power combiner and
ditto bidirectional power... A distribution network which can be an active power splitter or an active power combiner or alternatingly power splitter and such a power combiner. The power... |
| US-6,900,694 |
High frequency power amplifier module and wireless communication apparatus The number of components of a high frequency power amplifier is reduced. A bias resistance ratio is adjusted in accordance with a change in the threshold voltage... |
| US-6,900,693 |
Power amplifying apparatus and radio communications apparatus using same By extracting a portion of RF signals from an input side of a multistage RF amplifier with a detector, and converting extracted signals into envelope signals,... |
| US-6,900,692 |
High efficiency power amplifier with multiple power modes A multiple power mode amplifier provides a low and a high power mode without using switches. This amplifier may be used in RF applications such as mobile... |
| US-6,900,691 |
Semiconductor integrated circuit A semiconductor integrated circuit includes a first pad mounted on a main surface of a semiconductor substrate, a second pad mounted on the main surface and... |
| US-6,900,690 |
Low-power high-performance integrated circuit and related methods An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the... |
| US-6,900,689 |
CMOS reference voltage circuit A CMOS reference voltage circuit, preferably formed on a semiconductor integrated circuit, and outputting a reference voltage having a temperature-independent... |
| US-6,900,688 |
Switch circuit A switch circuit includes an input terminal, an internal circuit, and first and second MOS transistors. The input terminal receives an input signal. The internal... |
| US-6,900,687 |
Circuitry and method to provide a high speed comparator for an input stage
of a low-voltage differential signal... An input stage circuit for an LVDS circuit. The input stage has a folded cascode that receives input signals. The folded cascode has a first input circuit and a... |
| US-6,900,686 |
Analog switching circuit An analog switching circuit selects one of a first pair of differential outputs of a first circuit having a first common mode voltage and a second pair of... |
| US-6,900,685 |
Tunable delay circuit A delay circuit delays an input signal to produce an output signal. The input and output signals have a delay which is based on a signal relationship between the... |
| US-6,900,684 |
Pulse processing circuit and frequency multiplier circuit PMOS transistors P1-Pn and PMOS transistors P1'-Pn' are respectively connected in series between a supply voltage terminal VD and output terminals OUTB, while... |
| US-6,900,683 |
Apparatus and method for generating a predetermined time delay in a
semiconductor circuit A semiconductor arrangement is provided for generating a predetermined time delay. Two clocks are connected to two parallel, redundant semi-conductor circuits... |
| US-6,900,682 |
Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator.... |
| US-6,900,681 |
Phase interpolator and receiver for adjusting clock phases into data phases An aspect of the present invention provides a phase interpolator for adjusting a phase of differential clock signals of a receiver to a phase of a data from a... |
| US-6,900,680 |
Clock controlling method and circuit A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input... |
| US-6,900,679 |
Digital phase control circuit The digital phase control circuit of the present invention is provided with: voltage-controlled delay line VCDL1 in which differential buffers G1-G10 having a... |
| US-6,900,678 |
Delay lock circuit using bisection algorithm and related method A method for performing a delay lock to generate a second clock according to a first clock and to synchronize the second clock with the first clock is provided.... |
| US-6,900,677 |
Differential charge pump and method therefor, and phase locked loop and
method therefor using the pump and method Disclosed is a differential charge pump and a method for pumping the same, and a phase locked loop using the pump and a method for phase locked looping. The... |
| US-6,900,676 |
Clock generator for generating accurate and low-jitter clock A clock generator has a clock generating circuit, a phase difference detection circuit, and a control signal generating circuit. The clock generating circuit has... |
| US-6,900,675 |
All digital PLL trimming circuit In one set of embodiments, the invention comprises a system and method for automatically trimming the center frequency of a VCO in a PLL. The trimming may be... |
| US-6,900,674 |
Method and circuitry for phase align detection in multi-clock domain In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations,... |
| US-6,900,673 |
Microcontroller unit A micro-controller adjustably provides a scanning frequency for operating a driver for an ultrasonic device. The frequency is adjusted within a defined range... |
| US-6,900,672 |
Driver circuit having a slew rate control system with improved linear ramp
generator including ground Methods and structures for ensuring the highly linear discharge of a capacitor used for slew rate control of a power driving stage from a maximum voltage to a... |
| US-6,900,671 |
Current-voltage conversion circuit It is an object of the present invention to provide a current-voltage conversion circuit in which the sensitivity varies in accordance with the amplitude of the... |
| US-6,900,670 |
Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3 MOS) logic fabricated in conventional CMOS process... |
| US-6,900,669 |
Area efficient on-chip timeout generator with low temperature and low
supply voltage dependency An area-efficient fully integrated BiCMOS analog time delay circuit with low-power supply requirements provides delays as long as two milliseconds. An ultralow... |
| US-6,900,668 |
High speed single ended sense amplifier with built-in multiplexer A first sense amp circuit includes a pre-charge circuit, a keeper circuit, a select device and a driver device. The pre-charge circuit coupled to an input data... |
| US-6,900,667 |
Logic constructions and electronic devices The invention includes a TFT-based logic circuit construction. Such construction includes a pair of first transistor devices, and a pair of second transistor... |
| US-6,900,666 |
Dual threshold voltage and low swing domino logic circuits A domino logic circuit is configured to reduce power consumption. In a first embodiment, a sleep switch grounds the dynamic node during sleep mode. In a second... |
| US-6,900,665 |
Transfer of digital data across asynchronous clock domains A method and circuit for transferring multiple bits of data across asynchronous clock domains is provided. The method includes detecting a change in a status bit... |
| US-6,900,664 |
Method and system for intelligent bi-direction signal net with dynamically
configurable input/output cell A preferred embodiment includes a distributed network of a plurality of dynamically configurable bi-directional input/output (I/O) cells, each including a... |
| US-6,900,663 |
Low voltage differential signal driver circuit and method Embodiments of the present invention relate to a low voltage differential signal driver (LVDS) circuit which comprises a current source, logic controlled... |
| US-6,900,662 |
Level translator circuit for power supply disablement A level translator circuit for use between a transmitting voltage potential circuit and a receiving voltage potential circuit is disclosed. The translator... |
| US-6,900,661 |
Repairable finite state machines A method and respective hardware logic circuit for implementing partially programmable Finite State Machines in the hardware of digital systems which use finite... |
| US-6,900,660 |
IC with digital and analog circuits and mixed signal I/O pins An integrated circuit providing mixed signal processing. I/O pin interface circuits include logic gates and other circuits for processing digital and analog... |
| US-6,900,659 |
Methods and apparatus for loading data into a plurality of programmable
devices There is disclosed a method for loading data into a plurality of programmable devices connected in parallel to one or more data lines comprising the steps of:... |
| US-6,900,658 |
Null convention threshold gate A NULL convention-threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an... |
| US-6,900,657 |
Stall detection circuit and method A stall detection circuit and method for a stepper motor. The circuit has an H-bridge configuration with an additional circuit pathway to ground being connected... |
| US-6,900,656 |
Method of testing an integrated circuit and an integrated circuit test
apparatus A method of testing an Integrated Circuit (IC) and an IC test apparatus is provided. In one embodiment, the method of testing includes (1) applying a voltage to... |
| US-6,900,655 |
Determination of whether integrated circuit is acceptable or not in
wafer-level burn-in test A plurality of integrated circuits are inspected for their characteristics, after applying uniform stresses to the integrated circuits from common ... |
| US-6,900,654 |
Method and apparatus for evaluating a known good die using both wire bond
and flip-chip interconnects Wire bond pad and solder ball or controlled collapse chip connections C4 are combined on a planar surface of a an integrated circuit device to provide a die.... |
| US-6,900,653 |
Needle fixture of a probe card in semiconductor inspection equipment and
needle fixing method thereof A needle fixture of a probe card and a needle fixing method in semiconductor inspection equipment include a needle fixture of a probe card in semiconductor... |
| US-6,900,652 |
Flexible membrane probe and method of use thereof A measuring apparatus for measuring a semiconductor wafer, or a film or coating thereon, includes an electrically conductive wafer chuck and a probe having a... |
| US-6,900,651 |
Electroconductive contact unit assembly A low electric resistance is accomplished because there are no parts connecting different components as opposed to the arrangement using an electroconductive... |
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