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| Patent # | Description |
|---|---|
| US-6,901,506 |
Maximal tile generation technique and associated methods for designing and
manufacturing VLSI circuits A non-maximal arrangement of component tiles is reconfigured into a maximal arrangement. For each identified active segment of a first span not having a matching... |
| US-6,901,505 |
Instruction causing swap of base address from segment register with address
from another register A processor is described which executes an instruction defined to swap the contents of at least one special purpose register (e.g. an MSR or a segment register)... |
| US-6,901,504 |
Result forwarding of either input operand to same operand input to reduce
forwarding path Embodiments are provided in which result forwarding for each execution unit in a processor is implemented for only one operand input of the execution unit. If... |
| US-6,901,503 |
Data processing circuits and interfaces An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The... |
| US-6,901,502 |
Integrated circuit with CPU and FPGA for reserved instructions execution
with configuration diagnosis A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein... |
| US-6,901,501 |
Data processor In a memory access process, by identifying the types of memories that can be activated without reducing operating speed and by reducing power consumption, a data... |
| US-6,901,500 |
Method and apparatus for prefetching information and storing the
information in a stream buffer A system for prefetching information from a computer storage includes a central processing unit operable to transmit to a transfer bus a memory transfer request... |
| US-6,901,499 |
System and method for tracking data stored in a flash memory device A flash driver tracks data stored in a flash memory device through the use of logical-to-physical sector mapping. The mapping is stored in a data structure and... |
| US-6,901,498 |
Zone boundary adjustment for defects in non-volatile memories A non-volatile memory is divided into logical zones by the card controller in order reduce the size of the data structures it uses for address translation. Zone... |
| US-6,901,497 |
Partition creating method and deleting method A size of a partition to be created on a storage device is limited to a size of m to n-th power, where m and n are natural numbers. In creation of the partition,... |
| US-6,901,496 |
Line rate buffer using single ported memories for variable length packets A network interface card is provided. The network interface card includes a plurality of pipelined processors. Each of the pipelined processors includes an input... |
| US-6,901,495 |
Cache memory system allowing concurrent reads and writes to cache lines to
increase snoop bandwith A cache memory includes a plurality of memory chips, or other separately addressable memory sections, which are configured to collectively store a plurality of... |
| US-6,901,494 |
Memory control translators According to one aspect of the invention, a method is provided in which one or more write commands and their corresponding write data are received from a first... |
| US-6,901,493 |
Method for protecting data of a computer system In a method for protecting data of a computer system having a hard drive with an operating system stored on a first partition thereof, the operating system is... |
| US-6,901,492 |
Electronic device for reducing interleaving write access conflicts in
optimized concurrent interleaving... An electronic device may include a source memory device partitioned into N elementary source memories for storing a sequence of input data sets, and a processor... |
| US-6,901,491 |
Method and apparatus for integration of communication links with a remote
direct memory access protocol In one embodiment, a server is provided. The server includes multiple application processor chips. Each of the multiple application processor chips includes... |
| US-6,901,490 |
Read/modify/write registers The present invention may provide a digital memory circuit comprising a plurality of multi-bit registers, a memory circuit interface, and a logic circuit. The... |
| US-6,901,489 |
Streaming input engine facilitating data transfers between application
engines and memory A system includes a memory, a sequencer, and a set of application engines in communication with the sequencer and memory. The set of application engines includes... |
| US-6,901,488 |
Compute engine employing a coprocessor A compute engine includes a central processing unit coupled to a coprocessor. The coprocessor includes a sequencer coupled to a set of application engines for... |
| US-6,901,487 |
Device for processing data by means of a plurality of processors A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data... |
| US-6,901,486 |
Method and system for optimizing pre-fetch memory transactions A method of determining whether to issue a pre-fetch transaction in a memory control system comprising generating a pre-fetch threshold dependent on a demand... |
| US-6,901,485 |
Memory directory management in a multi-node computer system A computer system includes a home node and one or more remote nodes coupled by a node interconnect. The home node includes a local interconnect, a node... |
| US-6,901,484 |
Storage-assisted quality of service (QoS) Storage-Assisted QoS. To provide storage-assisted QoS, a discriminatory storage system able to enforce a service discrimination policy within the storage system... |
| US-6,901,483 |
Prioritizing and locking removed and subsequently reloaded cache lines A method for selecting a line to replace in an inclusive set-associative cache memory system which is based on a least recently used replacement policy but is... |
| US-6,901,482 |
Managing ownership of a full cache line using a store-create operation A system includes a plurality of processing clusters and a snoop controller. A first processing cluster in the plurality of processing clusters includes a first... |
| US-6,901,481 |
Method and apparatus for storing transactional information in persistent
memory A method and apparatus for storing transactional information in persistent memory. In one embodiment, the invention features a persistent volatile memory and an... |
| US-6,901,480 |
Method and apparatus for reconfiguring striped logical devices in a disk
array storage A method and apparatus for enabling an on-line reconfiguration of striped data in a disk array storage device. A replicated copy of the striped logical device is... |
| US-6,901,479 |
Disk array apparatus for and method of expanding storage capacity
dynamically A controller retrieves effective logical addresses sequentially according to a copy of an address translation table at the time of the start of storage capacity... |
| US-6,901,478 |
Raid system and mapping method thereof A system having RAID levels includes a storage medium, a memory and a CPU. The storage medium has at least two disks. The memory stores a striping zone... |
| US-6,901,477 |
Provision of a victim cache within a storage cache hierarchy Apparatus, methods, and program products for storing data address a first cache and a second cache. The second cache is capable of operating in a first mode... |
| US-6,901,476 |
Variable key type search engine and method therefor A system and method for storing arranged data in a memory, and for extracting the data therefrom, the system including: (a) a random access memory (RAM)... |
| US-6,901,475 |
Link bus for a hub based computer architecture A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is... |
| US-6,901,474 |
Application programming interface for data transfer and bus management over
a bus structure In a first embodiment, an applications programming interface (API) implements and manages isochronous and asychronous data transfer operations between an... |
| US-6,901,473 |
Apparatus and method for configuring an external device The present invention provides a method and apparatus for configuring an external device. The method comprises receiving configuration information, and providing... |
| US-6,901,472 |
Data-processing unit with a circuit arrangement for connecting a first
communications bus with a second... A data processing configuration with a first circuit configuration (1) that connects a first communication bus (2) with a second communication bus (3). The first... |
| US-6,901,471 |
Transceiver macrocell architecture allowing upstream and downstream
operation A system wherein a signal over a Universal Serial Bus (USB) interface is received by a receiver component. A mixed signal block utilizes a mixed signal interface... |
| US-6,901,470 |
Data input/output system A data I/O system includes first and second function blocks connected to a system bus, which allows the function blocks to communicate with a processor. Each... |
| US-6,901,469 |
Communication control apparatus using CAN protocol A communication control apparatus for performing an arbitration when a collision of frames occurs on a bus has a plurality of message boxes. Each message box... |
| US-6,901,468 |
Data storage system having separate data transfer section and message
network having bus arbitration A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer... |
| US-6,901,467 |
Enhancing a PCI-X split completion transaction by aligning cachelines with
an allowable disconnect boundary's... A method for processing a PCI-X transaction in a bridge is disclosed, wherein data is retrieved from a memory device and is stored in a bridge then delivered to... |
| US-6,901,466 |
Apparatus for extending the available number of configuration registers A method for expanding the number of configuration registers available in a computer system. Unused configuration registers that correspond to non-existent... |
| US-6,901,465 |
Data transfer control device, electronic equipment, and data transfer
control method A data transfer control device using USB (a first bus), the end of a data phase (data transport: transfer of all the data) during an OUT transaction is... |
| US-6,901,464 |
Puck interface adapter including drivers for interfacing serial device to
host wherein puck implements command... The invention provides a plug-and-work sensor interface device named "puck" for fast and easy deployment of various types of serial devices, which include... |
| US-6,901,463 |
Method and device for linking work requests with completion queue entries A method for linking work requests in a work queue with entries on a queue of completed requests. For each work queue, a tracking list is created. Each tracking... |
| US-6,901,462 |
Receiving apparatus and flow control method therefor and transmitting
apparatus and flow control method therefor A receiving apparatus constructed to store data received from a network in a buffer and read the data in the buffer based on a reference clock, has a detecting... |
| US-6,901,461 |
Hardware assisted ATA command queuing One embodiment involves having a processor writing disk drive command information for a number of data transactions to cacheable system memory. The processor... |
| US-6,901,460 |
Competitive management system and method for external input/output devices
and recording medium recording program The present invention provides a competitive management system for external input/output devices in which there is no need for each service to make the... |
| US-6,901,459 |
PROTOCOL FOR TRANSMITTING A PLURALITY OF MULTIPLE EXCHANGE LOGIC FLOW OF
COMMAND/RESPONSE PAIRS ON A SINGLE... An existing active base logic flow between a master transceiver and a slave transceiver, is selected as reference logic flow wherein is generated a set of... |
| US-6,901,458 |
Multi-mode SCSI backplane and detection logic The present invention includes a multi-mode SCSI backplane and a detection logic that is used in conjunction with the backplane. In this invention, the SCSI... |
| US-6,901,457 |
Multiple mode communications system An universal and detachable low cost data storage system adaptable to different communication protocols. Particularly, the storage system can be attached to... |
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