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| Patent # | Description |
|---|---|
| US-6,924,696 |
Method and apparatus for common-mode level shifting A circuit in accordance with the invention comprises a differential amplifier; and a direct current (DC) source coupled with the differential amplifier. The DC... |
| US-6,924,695 |
Power supply processing for power amplifiers The present invention, generally speaking, uses multiple selectable power supply paths, a saturation detector, or combinations of the same to achieve efficient... |
| US-6,924,694 |
Switch circuit A switch circuit formed on a semiconductor substrate, comprising: a first terminal to which a signal of transmission object is inputted; a second terminal from... |
| US-6,924,693 |
Current source self-biasing circuit and method Method and apparatus for a nonlinear current circuit element are described, and method and apparatus using the nonlinear current circuit element in ... |
| US-6,924,692 |
Voltage reference generator According to an embodiment of the invention, a method and apparatus for dynamic reference voltage adjustment are described. According to one embodiment, a... |
| US-6,924,691 |
Rectifying charge storage device with sensor A rectifying charge storage device, consisting of a rectifier and capacitor which share common elements, includes a sensor responsive to a monitored parameter... |
| US-6,924,690 |
Voltage switching circuit A voltage switching circuit is disclosed which is constructed from a minimum number of transistors and prevents the threshold voltage margin from being lowered... |
| US-6,924,689 |
Level shifter reference generator A core voltage to input output voltage level shifter of the type that uses a reference voltage source to generate a reference voltage to limit a drain voltage on... |
| US-6,924,688 |
Rectifying charge storage device with antenna A composite rectifying charge storage device, consisting of a rectifier and capacitor which share common elements, is combined in a circuit with an antenna for... |
| US-6,924,687 |
Voltage tolerant circuit for protecting an input buffer An invention is disclosed for protecting an input buffer. A current from a p-supply to an input buffer is lowered when an input voltage to the input buffer is... |
| US-6,924,686 |
Synchronous mirror delay (SMD) circuit and method including a counter and
reduced size bi-directional delay line A synchronous mirror delay (SMD)includes a model delay line that is coupled to a bi-directional delay line. In operation, an initial edge an input clock signal... |
| US-6,924,685 |
Device for controlling a setup/hold time of an input signal The device for controlling a setup/hold time of an input signal can change a setup/hold time of various control signals applied from an input buffer without... |
| US-6,924,684 |
Counter-based phase shifter circuits and methods with optional duty cycle
correction Phase shifter circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock... |
| US-6,924,683 |
Edge accelerated sense amplifier flip-flop with high fanout drive
capability Flip-flop devices provide fast clock-to-Q timing that exploits the pulsed nature of outputs generated by a clocked sense amplifier. These flip-flop devices... |
| US-6,924,682 |
Latch circuit with metastability trap and method therefor Methods and apparatus are provided for trapping metastability events to provide a metastable-free output signal. Values of an input signal compared to at least... |
| US-6,924,681 |
Efficient pulse amplitude modulation transmit modulation Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408... |
| US-6,924,680 |
DLL circuit for stabilization of the initial transient phase A DLL circuit for phase matching of a periodic input signal, having a variable delay unit, having a delay element and having a regulation unit which has a... |
| US-6,924,679 |
Power supply control device, semiconductor device and method of driving
semiconductor device A power supply voltage control apparatus including an input signal generation circuit of wide uses or a small-sized monitor circuit of a novel configuration, and... |
| US-6,924,678 |
Programmable phase-locked loop circuitry for programmable logic device A phase-locked loop ("PLL") for use in a programmable logic device ("PLD") is constructed with modular components, which may be digital, and which may be... |
| US-6,924,677 |
Phase-locked loop integrated circuits that support clock signal updates
during dead zone compensation time... PLL integrated circuits include a charge pump having first and second input terminals that are configured to receive UP and DOWN control signals, respectively. A... |
| US-6,924,676 |
Conditioned and robust ultra-low power power-on reset sequencer for
integrated circuits A power-on reset (POR) circuit determines when integrated circuit voltages and/or currents have reached predetermined levels and provides trigger signals to... |
| US-6,924,675 |
Buffer device A buffer device includes a plurality of latch stages which each have a latch device and a multiplexer. At least the multiplexer of the first latch stage on the... |
| US-6,924,674 |
Composite source follower A folded cascode device senses the drain current of a source follower, and a current mirror device multiplies the sensed drain current for application to an... |
| US-6,924,673 |
Input/output buffer for protecting a circuit from signals received from
external devices and method of use An input/output buffer that protects a circuit from voltage signals provided from an external device. The input/output buffer includes a reference power... |
| US-6,924,672 |
CMOS comparator output stage and method A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first... |
| US-6,924,671 |
General-purpose logic module and cell using the same A general-purpose logic module is composed of: a first inverter 10 in which an input terminal is connected to a first node T1; a second node T2 connected to an... |
| US-6,924,670 |
Complementary input dynamic muxed-decoder A muxed-decoder circuit including multiple complementary input dynamic circuits and an AND logic gate. Each complementary input dynamic circuit includes a... |
| US-6,924,669 |
Output buffer circuit and control method therefor An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform.... |
| US-6,924,668 |
Differential to single-ended logic converter The present invention is a converter stage for converting a differential logic input signal and a corresponding common mode differential logic signal each having... |
| US-6,924,667 |
Level shifting and level-shifting amplifier circuits Level shifting and amplified level shifting circuit topologies are provided that include two or more level shifting or amplified level shifting circuits. The... |
| US-6,924,666 |
Integrated logic circuit and hierarchical design method thereof Modules 14 to 18 are disposed in a chip 10, and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14,... |
| US-6,924,665 |
Logic device re-programmable without terminating operation A logic device re-programmable without terminating operation. In the logic device, a logic circuit is configured and maintained based on logic circuit... |
| US-6,924,664 |
Field programmable gate array A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed... |
| US-6,924,663 |
Programmable logic device with ferroelectric configuration memories A programmable logic device with ferroelectric configuration memories storing multiple configuration data sets. The device has programmable logic blocks,... |
| US-6,924,662 |
Configurable cell for customizable logic array device This invention discloses a cell forming part of a customizable logic array device, the cell including at least first (34) and second multiplexers, each having a... |
| US-6,924,661 |
Power switch circuit sizing technique An integrated circuit structure has at least one voltage island and a pattern of power switches within the voltage island. The pattern determines the number of... |
| US-6,924,660 |
Calibration methods and circuits for optimized on-die termination Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via... |
| US-6,924,659 |
Programmable signal termination for FPGAs and the like A termination scheme for the I/O circuitry of a programmable device, such as a field-programmable gate array (FPGA), has programmable resistors switchably... |
| US-6,924,658 |
Device and method for checking signal transmission quality of circuit board A device and a method are used to check signal transmission quality of a circuit board. The circuit board communicates a source device with a destination device... |
| US-6,924,657 |
Real-time in-line testing of semiconductor wafers An apparatus and method for the real-time, in-line testing of semiconductor wafers during the manufacturing process. In one embodiment the apparatus includes a... |
| US-6,924,656 |
Method and apparatus for testing BGA-type semiconductor devices A plurality of semiconductor devices is placed in pockets of a tray with terminal surfaces facing upward. Positions of bump terminals of the semiconductor... |
| US-6,924,655 |
Probe card for use with microelectronic components, and methods for making
same The present disclosure provides probe cards which may be used for testing microelectronic components, including methods of making and using such probe cards. One... |
| US-6,924,654 |
Structures for testing circuits and methods for fabricating the structures One embodiment of the present invention is a structure useful for testing circuits that includes: (a) a flexible substrate having contactors on a first side and... |
| US-6,924,653 |
Selectively configurable microelectronic probes Microelectronic components are commonly tested with probe cards. Certain aspects of the invention provide alternative probes, probe cards, and methods-of testing... |
| US-6,924,652 |
Method for determining optimal degree of vulcanization and optimal content
of constituent ingredient of... The present invention relates to a method for evaluating the crosslink degree of a vulcanized sample in real time during a vulcanization process or diagnosing... |
| US-6,924,651 |
Printed board inspecting apparatus A printed board inspecting apparatus includes: an input unit for inputting a pulse from a first signal line; a receiving unit for receiving a voltage induced in... |
| US-6,924,650 |
Device for generator diagnosis with built-in rotor In a device for the investigation of components of a generator which border on a machine air gap (29) between stator and rotor (22), with the rotor (22) built... |
| US-6,924,649 |
Sensor read out A circuit and a method to measure continuously the resistance of variable resistors in series as e.g. potentiometers within a sensor, used for e.g. a joystick,... |
| US-6,924,648 |
Method for identifying risks as a result of stray currents A method is for identifying risks as a result of stray currents which flow to ground from a rail which returns a traction current in a track with a DC power... |
| US-6,924,647 |
Fault location method and device The present invention relates to a method for calculating the distance to fault in a section of a power transmission network, which section is arranged with line... |
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