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| Patent # | Description |
|---|---|
| US-6,925,550 |
Speculative scheduling of instructions with source operand validity bit and
rescheduling upon carried over... A method and apparatus to execute data speculative instructions in a processor comprising at least one source register, each source register comprising a bit to... |
| US-6,925,549 |
Asynchronous pipeline control interface using tag values to control passing
data through successive pipeline stages An apparatus and method for externally managing data within an asynchronous pipeline. The asynchronous pipeline over which control is sought includes a data path... |
| US-6,925,548 |
Data processor assigning the same operation code to multiple operations A data processor can assign a greater number of operations to instruction codes with shorter length, thereby implementing high performance, high code efficiency... |
| US-6,925,547 |
Remote address translation in a multiprocessor system A method of performing remote address translation in a multiprocessor system includes determining a connection descriptor and a virtual address at a local node,... |
| US-6,925,546 |
Memory pool configuration system A memory partitioning system for memory of an embedded or auxiliary processor is described. Memory regions with different attributes are formed, having specified... |
| US-6,925,545 |
Configuring file structures and file system structures in a memory device The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a... |
| US-6,925,544 |
Packet buffer memory with integrated allocation/de-allocation circuit A buffer memory with a memory allocation and de-allocation circuit. The buffer memory has an address space divided into address blocks and a memory address space... |
| US-6,925,543 |
Burst transfer memory The present invention provides a burst transfer memory comprising a first memory having a cell array arranged in a matrix, a second memory which has a cell array... |
| US-6,925,542 |
Memory management in a data processing system Memory management in a data processing system (10) is achieved by using one or more timing bits (54) to specify a timing parameter of a memory (18, 19, 34). To... |
| US-6,925,541 |
Method and apparatus for managing replication volumes Replication of volumes is facilitated by tools which provide and manage a pool of mirror volumes. Primary (or production) volumes containing user provided data... |
| US-6,925,540 |
Systems and methods for chassis identification A identification system comprising at least one non-volatile memory device containing identification data, a communication bus for the memory device that is... |
| US-6,925,539 |
Data transfer performance through resource allocation Method and apparatus for transferring data between a host device and a data storage device having a first memory space and a second memory space. The first... |
| US-6,925,538 |
Extending the functionality of a multi-functional apparatus A multi-functional apparatus of all-in-one type has a plurality of functions and comprises a plurality of devices having respective functions, a designation... |
| US-6,925,537 |
Multiprocessor cache coherence system and method in which processor nodes
and input/output nodes are equal... A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an... |
| US-6,925,536 |
Cache coherence directory eviction mechanisms for unmodified copies of
memory lines in multiprocessor systems Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the... |
| US-6,925,535 |
Program control flow conditioned on presence of requested data in cache
memory Method and apparatus for conditioning program control flow on the presence of requested data in a cache memory. In a data processing system that includes a cache... |
| US-6,925,534 |
Distributed memory module cache prefetch One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The... |
| US-6,925,533 |
Virtual disk image system with local cache disk for iSCSI communications A system and method for caching data received over a network connection comprising: a target device for receiving requests for routing data packetized for... |
| US-6,925,532 |
Broadcast system in disk array controller A disk array controller connected in a star configuration with a plurality of interfaces each having a processor, a shared memory connected to the interfaces by... |
| US-6,925,531 |
Multi-element storage array A self-contained data storage module receives a data request conforming to a first standard. The data request is translated into a second standard. At least one... |
| US-6,925,530 |
Initialization of a storage system A storage array comprised of a number of storage drives is provided with a controller to control zero initialization of the storage drives. The zero ... |
| US-6,925,529 |
Data storage on a multi-tiered disk system A method and a computer usable medium including a program for operating disks having units, comprising: providing a first tier of at least one disk, the first... |
| US-6,925,528 |
Floating virtualization layers A virtual stored data management system is provided. In one embodiment, the management system includes one or more hosts and a plurality of data storage elements... |
| US-6,925,527 |
Storage control apparatus and method for compressing data for disk storage A method of managing compressed data including a cache segment generating operation generating cache segments each representing data that is obtained by... |
| US-6,925,526 |
Method and apparatus for servicing mixed block size data access operations
in a disk drive data storage device Write operations less than full block size (short block writes) are internally accumulated while being written to disk in a temporary cache location. Once... |
| US-6,925,525 |
Data storage management system and method The present invention provides a virtual automated cartridge system (ACS) and data storage device management method which incorporates a temporary data buffer... |
| US-6,925,524 |
Associated content storage system A relocation system to associatively search a database lookup table with a search key to addressably retrieve a corresponding associate content table record as a... |
| US-6,925,523 |
Managing monotonically increasing counter values to minimize impact on
non-volatile storage Reducing writes to non-volatile storage in a system for tracking sequence numbers in a communications protocol. In a system which tracks sequence numbers, a... |
| US-6,925,522 |
Device and method capable of changing codes of micro-controller A device and method capable of changing codes of a micro-controller comprises a micro-controller, an address latch, a flash memory, a static random access memory... |
| US-6,925,521 |
Scheme for implementing breakpoints for on-chip ROM code patching The present invention relates to a system and a method for preventing address conflicts when establishing breakpoints and applying one or more patches to code... |
| US-6,925,520 |
Self-optimizing crossbar switch A crossbar switch is disclosed. The crossbar switch comprises a plurality of input sorting units and a plurality of merge and interleave units. Each input... |
| US-6,925,519 |
Automatic translation from SCSI command protocol to ATA command protocol A device generally comprising a first circuit and a second circuit. The first circuit may be configured to (i) communicate with a host via a first bus (ii) using... |
| US-6,925,518 |
Bridging system for interoperation of remote groups of devices A bridging system for a communication system comprises a first gateway (107) and a second gateway (108) arranged to communicate with each other. Each gateway... |
| US-6,925,517 |
Bus for supporting plural signal line configurations and switch method
thereof A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation... |
| US-6,925,516 |
System and method for providing an improved common control bus for use in
on-line insertion of line replaceable... There is disclosed a system and method for providing an improved common control bus for use in the on-line insertion of line replaceable units (such as circuit... |
| US-6,925,515 |
Producer/consumer locking system for efficient replication of file data In a distributed file system the distributed storage management is made useful to a variety of applications. Multiple quality of service options are provided... |
| US-6,925,514 |
Multi-protocol bus system and method of operation thereof A multi-protocol bus system and a method of operating the same. In one embodiment, the multi-protocol bus system includes a plurality of protocol indicators... |
| US-6,925,513 |
USB device notification A method of notifying clients of a change in a USB (Universal Serial Bus) including a first client requesting notification of a first change in the USB,... |
| US-6,925,512 |
Communication between two embedded processors A system including at least two processing units embedded on a chip able to communicate with each other and to generally independently control access to data... |
| US-6,925,511 |
Disk array control apparatus and control data transfer method using the
same A disk array control apparatus includes a plurality of disk array control units for controlling data transfer between a plurality of host computers and a... |
| US-6,925,510 |
Peripheral or memory device having a combined ISA bus and LPC bus A peripheral or memory device has a bus, a first bus decoder circuit coupled to the bus for decoding a first type of bus signal, and a second bus decoder circuit... |
| US-6,925,509 |
Outputting a packet of character data information of an electronic program
guide compliant with IEEE 1394... The present invention relates to an image printing apparatus for printing character data information of an electronic program guide added to externally inputted... |
| US-6,925,508 |
Recording method from improving interrupted interference by checking size
of main buffer and allocating... A recording method for improving interrupted interferences, for use in a recording apparatus. First, a buffer is allocated, and then, the size of the buffer is... |
| US-6,925,507 |
Device and method for processing a sequence of information packets The packets of the sequence are stowed away in a packets memory organized as a stack, in association with respective processing labels. The processing label... |
| US-6,925,506 |
Architecture for implementing virtual multiqueue fifos A circuit configured to provide a storage device comprising one or more virtual multiqueue FIFOs. The circuit is generally configured to operate at a preferred... |
| US-6,925,505 |
Method and device for data transmission control between IDE apparatuses A method and a device for controlling data transmission between IDE apparatuses allow an IDE controller of an IDE control device to send read control signal to... |
| US-6,925,504 |
Methods and apparatus for obtaining content from a content-originating
device within a computerized network A technique can be used to obtain content (e.g., a live feed, pre-positioned content, etc.) from a content-originating device (a content source). The technique... |
| US-6,925,503 |
Method and system for performing a longest prefix match search A method and system for finding a longest prefix match for a key in a computer network is disclosed. The method and system include providing a main engine and... |
| US-6,925,502 |
Methods and systems for improving data transmission rates having adaptive
protocols Methods and systems are provided to improve the data transmission rate of a system executing an network protocol such as TCP, by adapting the protocol according... |
| US-6,925,501 |
Multi-rate transcoder for digital streams Methods and apparatus are provided to produce a plurality of different rate output bitstreams from a common input bit stream. Overhead data is extracted from the... |
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