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| Patent # | Description |
|---|---|
| US-6,992,938 |
Methods and apparatuses for test circuitry for a dual-polarity
non-volatile memory cell Various apparatuses and methods are shown in which an integrated circuit includes a dual-polarity non-volatile memory cell and a test circuit. The test circuit... |
| US-6,992,937 |
Column redundancy for digital multilevel nonvolatile memory A digital multilevel bit memory array system comprises regular memory arrays and redundant memory arrays. A regular y-driver corresponds to each memory array to... |
| US-6,992,936 |
Semiconductor, memory card, and data processing system Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to... |
| US-6,992,935 |
Nonvolatile memory device efficiently changing functions of field
programmable gate array at high speed A switch section for changing the function of an FPGA is provided with a data latch circuit used for connection control. The data latch circuit includes program... |
| US-6,992,934 |
Read bitline inhibit method and apparatus for voltage mode sensing A multilevel memory system uses a source line driver circuit and a read bitline inhibit driver circuit to eliminate inhibit offset currents on unselected... |
| US-6,992,933 |
Programming verification method of nonvolatile memory cell, semiconductor
memory device, and portable... A method of verifying programming of a nonvolatile memory cell to a desired state, the method comprising the steps of: selecting first and second references... |
| US-6,992,932 |
Method circuit and system for read error detection in a non-volatile
memory array The present invention is a method, circuit and system for determining a reference voltage to be used in reading cells programmed to a given program state. Some... |
| US-6,992,931 |
System for trimming non-volatile memory cells A reference cell programming system comprising a memory device and a tester. The memory device includes a memory array having at least one non-volatile reference... |
| US-6,992,930 |
Semiconductor memory device, method for driving the same and portable
electronic apparatus A method for driving a semiconductor memory device includes a memory array having a plurality of memory cells arranged in rows and columns. Each memory cell... |
| US-6,992,929 |
Self-aligned split-gate NAND flash memory and fabrication process Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line... |
| US-6,992,928 |
Semiconductor memory device with an improved memory cell structure and
method of operating the same A semiconductor memory device includes a plurality of memory cells, each of which comprises a single pair of a volatile memory element and a non-volatile memory... |
| US-6,992,927 |
Nonvolatile memory cell An integrated nonvolatile memory circuit having a plurality of control devices. Separate devices execute distinct control, erase, write and read operations,... |
| US-6,992,926 |
Driver circuit for semiconductor storage device and portable electronic
apparatus A semiconductor storage device is provided with a gate electrode, a semiconductor layer, a gate insulating film sandwiched between the gate electrode and the... |
| US-6,992,925 |
High density semiconductor memory cell and memory array using a single
transistor and having counter-doped poly... A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate... |
| US-6,992,924 |
Magnetic memory and method for optimizing write current in a magnetic
memory The invention provides methods and apparatus for for determining and providing optimum write bit line current and write word line current in an MRAM. A single... |
| US-6,992,923 |
Single transistor type magnetic random access memory device and method of
operating and manufacturing the same A single transistor type magnetic random access memory device and a method of operating and manufacturing the same, wherein the single transistor type magnetic... |
| US-6,992,922 |
Cross point memory array exhibiting a characteristic hysteresis Providing a cross point memory array with memory plugs exhibiting a characteristic hysteresis. The memory plugs exhibit a hysteresis that, in the low resistive... |
| US-6,992,921 |
Magnetic random access memory and data write method for the same A magnetic random access memory includes a first write wiring line which runs in a first direction, a second write wiring line which has first and second regions... |
| US-6,992,920 |
Nonvolatile semiconductor memory device, and programming method and
erasing method thereof One end of each variable resistive element, which forms a memory array, in the same row is connected to the same word line and the other end of each variable... |
| US-6,992,919 |
All-metal three-dimensional circuits and memories A three-dimensional circuit and methods for fabricating such a circuit are described. The three-dimensional circuit includes a plurality of stacked levels on a... |
| US-6,992,918 |
Methods of increasing write selectivity in an MRAM MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory.... |
| US-6,992,917 |
Integrated circuit with reduced body effect sensitivity An integrated circuit (IC), random access memory on an IC and method of neutralizing device floating body effects. A floating body effect monitor monitors... |
| US-6,992,916 |
SRAM cell design with high resistor CMOS gate structure for soft error
rate improvement A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an... |
| US-6,992,915 |
Self reverse bias low-power high-performance storage circuitry and related
methods An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias... |
| US-6,992,914 |
Ferroelectric-type nonvolatile semiconductor memory A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first... |
| US-6,992,913 |
Ferroelectric storage device In the present invention, a polarization having a lower polarization level than a saturation polarization is caused in a ferroelectric capacitor by applying a... |
| US-6,992,912 |
Nonvolatile ferroelectric memory device having timing reference control
function and method for controlling the... A nonvolatile ferroelectric memory device amplifies a sensing voltage level of cell data with a CMOS threshold voltage reference in a main bitline, and decides... |
| US-6,992,911 |
Semiconductor memory device A semiconductor memory device of the invention has a first reference cell connected to a first bit line and a first word line to be controlled; a second... |
| US-6,992,910 |
Magnetic random access memory with three or more stacked toggle memory
cells and method for writing a selected cell A "toggling" type of magnetic random access memory (MRAM) has memory stacks arranged in the X-Y plane on the MRAM substrate with each memory stack having a... |
| US-6,992,909 |
Multi-bit ROM cell, for storing one of n>4 possible states and having
bi-directional read, an array of such... A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a... |
| US-6,992,908 |
Method and arrangement for charging intermediate circuit of frequency
converter A method and arrangement for charging an intermediate circuit of a frequency converter, the intermediate circuit of the frequency converter comprising one or... |
| US-6,992,907 |
Wave transformation method and device The present invention relates a waveform transformation method and apparatus. It uses multilevel transformation module in series, and the output voltages of... |
| US-6,992,906 |
Synthetic rectifiers A synthetic rectifier comprises a MOSFET and a control circuit to turn the MOSFET off and on as a synchronous rectifier. The control circuit senses the current... |
| US-6,992,905 |
High voltage generator having separate voltage supply circuit A high voltage generation circuit comprises a first boosting unit, a second boosting unit, a delay circuit which delays the output of the first boosting unit as... |
| US-6,992,904 |
Power converter module with a voltage regulating circuit A power converter module provides a regulated direct current voltage to a load, and includes a rectifier, a metal thin film capacitor, and a voltage regulating... |
| US-6,992,903 |
Method and apparatus for substantially reducing electrical earth
displacement current flow generated by wound... An energy transfer element having an energy transfer element input winding and an energy transfer element output winding. In one aspect, the energy transfer... |
| US-6,992,902 |
Full bridge converter with ZVS via AC feedback A soft-switched, full-bridge pulse-width-modulated converter and its variations provide zero-voltage-switching conditions for the turn-on of the bridge switches... |
| US-6,992,901 |
Shielding device for an electronic apparatus A shielding device includes an upper metal plate having downwardly extending and alternately disposed first and second plate sections and a lower metal plate... |
| US-6,992,900 |
Board unit To provide a board unit having an insertion-extraction handle locking structure with which a desired locking force can be easily generated and the locking force... |
| US-6,992,899 |
Power delivery apparatus, systems, and methods An apparatus and system, as well as fabrication methods therefor, may include a conductor attached to a carrier to bridge a contact field defined by a circuit... |
| US-6,992,898 |
Smart-card module with an anisotropically conductive substrate film A smart-card module is described which has a substrate film of an anisotropically conductive material and at least one semiconductor chip. The semiconductor chip... |
| US-6,992,897 |
Electronic apparatus and information processing apparatus There is provided an electronic apparatus that can solve the problem with the prior art that a removable electronic device is removed while the removable... |
| US-6,992,896 |
Stacked chip electronic package having laminate carrier and method of
making same A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier... |
| US-6,992,895 |
Heat controlled optoelectrical unit The present invention relates to heat control and cooling of an optoelectrical unit, which converts between electrical and optical signal formats. The... |
| US-6,992,894 |
Method and apparatus for EMI shielding An apparatus and method are provided for dissipating heat from an electronic component mounted in a conductive enclosure and for shielding electromagnetic... |
| US-6,992,893 |
Heat sink attachment An apparatus in one example comprises one or more adhesives that serve to provide at least primary attachment of a heat sink with one or more electrical... |
| US-6,992,892 |
Method and apparatus for efficient temperature control using a contact
volume A substrate holder for supporting a substrate, including an exterior supporting surface, a cooling component, a heating component positioned adjacent to the... |
| US-6,992,891 |
Metal ball attachment of heat dissipation devices An assembly including a heat dissipation device having an attachment surface, a substrate having an attachment surface, and a plurality of metal balls extending... |
| US-6,992,890 |
Heat sink A heat sink is provided. The heat sink comprises a hollow chassis having a contact face at a bottom portion thereof for attaching to an electronic component and... |
| US-6,992,889 |
Retention module, heat sink and electronic device It is an object of the present invention to provide a retention module, a heat sink and electronic apparatus for effectively the heat from a chip set. The... |
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