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| Patent # | Description |
|---|---|
| US-6,993,740 |
Methods and arrangements for automatically interconnecting cores in
systems-on-chip A method and algorithms for creating correct-by-construction interconnections among complex intellectual property (IP) cores with hundreds of pins. The methods... |
| US-6,993,739 |
Method, structure, and computer program product for implementing high
frequency return current paths within... A method, structure and computer program product are provided for implementing high frequency return current paths within electronic packages. Electronic package... |
| US-6,993,738 |
Method for allocating spare cells in auto-place-route blocks A method for placing spare cells into an auto-place-route (APR) block of an integrated circuit is disclosed. The list of functional cells to be included in the... |
| US-6,993,737 |
Leakage power optimization for integrated circuits A method for reducing leakage power in a system comprises determining the static probability for a signal in the system. If the static probability of the signal... |
| US-6,993,736 |
Pending bug monitors for efficient processor development and debug This invention addresses difficult issues encountered in simulations and design verification efforts on complex microprocessor/digital signal processor devices.... |
| US-6,993,735 |
Method of generating a test pattern for simulating and/or testing the
layout of an integrated circuit A method of generating a test pattern for simulating and/or testing the layout of an integrated circuit includes the steps of generating a set of test patterns... |
| US-6,993,734 |
Use of time step information in a design verification system The disclosed design verification system includes a verification engine to model the operation of an integrated circuit and to assess the model's adherence to a... |
| US-6,993,733 |
Apparatus and method for handling of multi-level circuit design data A system and method for implementation of look-ahead design methodology. Efficient debugging of a design is accomplished by evaluating the high level register... |
| US-6,993,732 |
Design of a pointerless BDD package A pointerless BDD package. A strict ordering is enforced on the BDD node identifiers and the advantageous consequences of that decision, such as a better memory... |
| US-6,993,731 |
Optimization of digital designs An application specific integrated circuit is optimized by translating a first representation of its digital design to a second representation. The second... |
| US-6,993,730 |
Method for rapidly determining the functional equivalence between two
circuit models This invention determines whether two circuit models have equivalent functionality. The method allows very fast comparison between two circuits taking advantage... |
| US-6,993,729 |
Method, system and program product for specifying a dial group for a
digital system described by a hardware... A statement in at least one hardware definition language (HDL) file specifies a plurality of design entities representing a functional portion of a digital... |
| US-6,993,728 |
Method of designing integrated circuit and apparatus for designing
integrated circuit An integrated circuit design method and an integrated circuit design apparatus, for increasing an efficiency of parallel processing of LSI design layout data... |
| US-6,993,727 |
MHP television device and GUI application An MHP television device including a user input and a GUI application for use in such a device wherein the GUI application maintains at least one notional wheel... |
| US-6,993,726 |
Methods and systems for document navigation using enhanced thumbnails A thumbnail image includes at least one selectable element. The selectable element may be selected, or the document as a whole may be selected. The selectable... |
| US-6,993,725 |
Display device and OSD controlling method for the same Disclosed is a display device including a display section for displaying a video signal, comprising: an OSD generating section adapted to generate a menu matrix... |
| US-6,993,724 |
Information processing apparatus, information processing method,
information processing program for performing... In an output setup to a device apparatus, when the contents of a plurality of setting items are changed in a lump by using a compound setup consisting of a... |
| US-6,993,723 |
Listing activities in a graphical user interface in a collaborative work
tool Architecture A system, method and program are provided for listing activities in a graphical user interface in a collaborative work tool framework. An activity window having... |
| US-6,993,722 |
User interface system methods and computer program products for
multi-function consumer entertainment appliances A user interface system, method and computer program product permits selection of predetermined device application modes in a television set system and checking... |
| US-6,993,721 |
Web channel guide graphical interface system and method In a system and method for enabling a user to navigate among a plurality of internet websites of interest to the user, the system includes a graphical user... |
| US-6,993,720 |
Apparatus and method for integrated software documentation A method executed by a computer under the control of a program includes the step of linking an application program module with a corresponding integrated... |
| US-6,993,719 |
System and method for animated character photo-editing interface and
cross-platform education icon A system and method for indicating suggested user responses is disclosed. The method includes loading an image into image-editing equipment. The method further... |
| US-6,993,718 |
Information processing method and apparatus Such a system is provided in which a map can be supplied to a user to permit the user to grasp the geography easily, if the address or the telephone number of an... |
| US-6,993,717 |
Data transformation system The present invention provides a system and a method for software conversions which maps and translates data from model reports to files formatted as either... |
| US-6,993,716 |
Frame rearrangement to support bidirectional languages in a Web
application A bidirectional frame processing system, method and apparatus. In accordance with the inventive arrangements, a preferred directional orientation can be... |
| US-6,993,715 |
Methods and systems for preparing extensible markup language (XML)
documents and for responding to XML requests Methods and systems for generating and sending an XML document are described. In a specific implementation, methods and systems for responding to an XML client... |
| US-6,993,714 |
Grouping and nesting hierarchical namespaces A group identifier represents an association between each of a number of different abbreviated namespace identifiers with a corresponding hierarchical namespace... |
| US-6,993,713 |
Web content management software utilizing a workspace aware JSP servlet The present invention is a method, system, and computer program product for editing dynamic web content. In accordance with the present invention, dynamic web... |
| US-6,993,712 |
System and method for facilitating user interaction in a browser
environment Techniques to support various operations (e.g., drag-and-drop, stretch) and data manipulation in a browser environment, e.g., to allow data for an object located... |
| US-6,993,711 |
Style-sheet output apparatus and method, and style-sheet output system Style sheets indicating layouts of a plurality of types are stored in a server. The user of a client computer selects the style sheet having the desired layout.... |
| US-6,993,710 |
Method and system for displaying changes of source code Methods and systems consistent with the present invention provide an improved software development tool which displays versions of source code with the... |
| US-6,993,709 |
Smart corner move snapping A method and apparatus of a layout editing system for arranging page structural elements in an electronic document. An electronic document having a grid provided... |
| US-6,993,708 |
System for automated generation and assembly of specifications documents
in CADD environments A method for automating the production of corroborative Textual Documentation (`Specifications Documents`) for CADD-based Design and Engineering disciplines... |
| US-6,993,707 |
Document placemarker A method of saving and retrieving a selected string on an HTML-based document. A cursor is placed at a location on the document. The number of HTML tags are... |
| US-6,993,706 |
Method, apparatus, and program for a state machine framework A programming framework is provided for designing and implementing software state machines. A state machine initializer may be created that defines the states,... |
| US-6,993,705 |
Cyclic redundancy check (CRC) parity check system and method A method for determining Cyclic Redundancy Check (CRC) parity of data, such data comprising a plurality of bytes, each one of the bytes having a parity bit, the... |
| US-6,993,704 |
Concurrent memory control for turbo decoders The concurrent memory control turbo decoder solution of this invention uses a single port main memory and a simplified scratch memory. This approach uses an... |
| US-6,993,703 |
Decoder and decoding method A decoder for performing log-sum corrections by means of a linear approximation, putting stress on speed, with a reduced circuit dimension without adversely... |
| US-6,993,702 |
Radix-N architecture for deinterleaver-depuncturer block A de-interleaver-de-puncturer architecture is scalable and capable of achieving a higher data throughput than that achievable using a conventional disjointed... |
| US-6,993,701 |
Row-diagonal parity technique for enabling efficient recovery from double
failures in a storage array A "row-diagonal" (R-D) parity technique reduces overhead of computing diagonal parity for a storage array adapted to enable efficient recovery from the... |
| US-6,993,700 |
System and method for generating forward error correction based alarms A system and method are provided for generating alarms from forward error correction (FEC) data in a G.709 network-connected integrated circuit. The method... |
| US-6,993,699 |
Turbo decoding apparatus and interleave-deinterleave apparatus In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a... |
| US-6,993,698 |
Turbocoding methods with a large minimum distance, and systems for
implementing them Turbocoding methods use a first RSC coder operating on sequences of binary data a, and a second RSC coder operating on binary sequences a* each obtained from a... |
| US-6,993,697 |
Method for obtaining from a block turbo-code an error correcting code of
desired parameters The present invention concerns a method for obtaining an error correcting code of a given first size (N), including a systematic information part of a given... |
| US-6,993,696 |
Semiconductor memory device with built-in self test circuit operating at
high rate A semiconductor memory device with a built-in self test circuit includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, an... |
| US-6,993,695 |
Method and apparatus for testing digital devices using transition
timestamps A method and apparatus for testing a device using transition timestamp are used to evaluate output signals from the device. The method comprises the steps of... |
| US-6,993,694 |
Deterministic bist architecture including MISR filter A filter for preventing uncertain bits output by test scan chains from being provided to a MISR is provided. The filter can include a gating structure for... |
| US-6,993,693 |
Analogue/digital interface circuit An analogue/digital interface circuit is disclosed in which an integral bistable circuit has its state changed by the arrival of an incoming analogue signal,... |
| US-6,993,692 |
Method, system and apparatus for aggregating failures across multiple
memories and applying a common defect... An integrated circuit includes a plurality of separate memory arrays each having a respective one of a plurality of inputs and a respective one of a plurality of... |
| US-6,993,691 |
Series connected TC unit type ferroelectric RAM and test method thereof Potential of a word line connected to any selected one of memory cells is lowered and potential of word lines connected to non-selected memory cells are raised.... |
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