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| Patent # | Description |
|---|---|
| US-7,046,563 |
Parallel compression test circuit of memory device A parallel compression test circuit of a memory device operates write drivers sequentially in a parallel compression test to disperse peak current and reduce... |
| US-7,046,562 |
Integrated circuit reset circuitry An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test... |
| US-7,046,561 |
Memory compiler redundancy An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory... |
| US-7,046,560 |
Reduction of fusible links and associated circuitry on memory dies The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among... |
| US-7,046,559 |
Semiconductor memory device capable of erasing or writing data in one bank
while reading data from another bank There is disclosed a semiconductor memory device including a memory cell array containing a plurality of banks each having one or more blocks, a data erase... |
| US-7,046,558 |
Method for controlling a nonvolatile memory A block comprises physical addresses 0, 1, 2, 3. In an initial state, all the physical addresses 0, 1, 2, 3, are in an erase state. When data LA0, LA1, LA2, LA3... |
| US-7,046,557 |
Flash memory Flash memory devices having control circuitry to decrease the magnitude of a source voltage of a first polarity during an erase period to increase the magnitude... |
| US-7,046,556 |
Twin insulator charge storage device operation and its fabrication method The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical... |
| US-7,046,555 |
Methods for identifying non-volatile memory elements with poor
subthreshold slope or weak transconductance A number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold... |
| US-7,046,554 |
Page buffer of flash memory device and data program method using the same Disclosed are a page buffer of a flash memory device and data program method using the same. After two data are sequentially stored in a main register (first... |
| US-7,046,553 |
Fast program to program verify method In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with... |
| US-7,046,552 |
Flash memory with enhanced program and erase coupling and process of
fabricating the same Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating... |
| US-7,046,551 |
Nonvolatile memories with asymmetric transistors, nonvolatile memories
with high voltage lines extending in the... Nonvolatile memory cells (110) are connected to a bitline (BL 170). The bitline is also connected to a source/drain region (620) of a transistor (610), a Y... |
| US-7,046,550 |
Cross-point memory architecture with improved selectivity A cross-point memory includes a plurality of memory cells, a plurality of global word lines, a plurality of local word lines, and a plurality of global bit... |
| US-7,046,549 |
Nonvolatile memory structure The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode.... |
| US-7,046,548 |
Techniques for reducing effects of coupling between storage elements of
adjacent rows of memory cells Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the... |
| US-7,046,547 |
Magnetic non-volatile memory coil layout architecture and process
integration scheme The invention relates to methods and apparatus that allow data to be stored in a magnetic memory cell, such as a giant magneto-resistance (GMR) cell, of a... |
| US-7,046,546 |
Semiconductor memory device A semiconductor memory device includes a first write wiring which has first to third running portions, first and second oblique running portions, the first and... |
| US-7,046,545 |
Semiconductor integrated circuit device including magnetoresistive effect
device and method of manufacturing... A semiconductor integrated circuit device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the... |
| US-7,046,544 |
SRAM cell with read-disturb immunity Described are small, efficient SRAM cells that are insensitive to read errors. SRAM cells in accordance with one embodiment include a pair of cross-coupled... |
| US-7,046,543 |
Semiconductor memory device with improved data retention characteristics Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting... |
| US-7,046,542 |
Semiconductor integrated circuit device A semiconductor integrated circuit device includes a plurality of memory cells which have two or more layout patterns and are arranged to make different patterns... |
| US-7,046,541 |
Semiconductor integrated circuit device There is disclosed a semiconductor integrated circuit device comprising a memory cell array including a memory cell having a ferroelectric capacitor having first... |
| US-7,046,540 |
Semiconductor integrated circuit device and information storage method
therefor A semiconductor integrated circuit device includes a cell array having a plurality of memory cells, a peripheral circuit which controls the cell array, and an... |
| US-7,046,539 |
Mechanical memory A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of... |
| US-7,046,538 |
Memory stacking system and method A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a... |
| US-7,046,537 |
Reduced signal swing in bit lines in a CAM A Content Addressable Memory device with a bit line that is driven between first and second voltage levels depending on the state of a logic signal applied... |
| US-7,046,536 |
Programable identification circuitry An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate... |
| US-7,046,535 |
Architecture for power modules such as power inverters Power converters such as power modules configured as inverters employ modularized approaches. In some aspects, semiconductor devices are thermally coupled... |
| US-7,046,534 |
DC/AC converter to convert direct electric voltage into alternating
voltage or into alternating current A DC/AC converter is disclosed having two DC voltage connections (1,2), between which are provided in a parallel circuit configuration, an intermediate energy... |
| US-7,046,533 |
DC/DC converter In a DC/DC converter having a plurality of DC/DC converters, to prevent faults in the circuit and the circuit elements constituting it even when the balance of... |
| US-7,046,532 |
Switching power supply A switching power supply wherein output voltage error detecting means detects the output voltage of DC-DC converters and generates an error signal, input voltage... |
| US-7,046,531 |
Transformerless static voltage inverter for battery systems A static inverter for a battery of elementary, current sources or cells electrically in series and a number N of intermediate voltage taps along the chain of... |
| US-7,046,530 |
Method and apparatus for current limiting of an output of a DC-to-DC
converter A method for current limiting of an output of a DC-to-DC converter begins by determining a current loading duty cycle of the output of the DC-to-DC converter... |
| US-7,046,529 |
Voltage adapter capable of conserving power consumption under standby mode A voltage adapter characterized by an advantage of reducing unnecessary power loss induced in standby mode operation and conserving the overall power consumption... |
| US-7,046,528 |
Load-dependent variable frequency voltage regulator A pulse width modulation voltage regulator comprises a pulse width modulation circuit and a control circuit. The control circuit is operable to reduce a pulse... |
| US-7,046,527 |
Power converter with ripple current cancellation using skewed switching
techniques The invention is an electrical power converter using multiple, high frequency switching elements where the individual switching elements are operated in a... |
| US-7,046,526 |
DC-AC converter, and method for supplying AC power First and second semiconductor switches which are activated alternately are provided between ends of a primary winding and a common potential point, wherein a DC... |
| US-7,046,525 |
Bidirectional flyback switch mode power supply (SMPS) The present invention relates to a bidirectional flyback switch mode power supply (SMPS), such as a bidirectional flyback converter, and a method for operating... |
| US-7,046,524 |
Power supply device comprising several switched-mode power supply units
that are connected in parallel The invention relates to a power supply device having several switch-mode power supplies connected in parallel to supply at least one consuming unit, each... |
| US-7,046,523 |
Core structure and interleaved DC--DC converter topology There is disclosed a core structure with a very low profile, high power density and lower losses. The disclosed design allows for a larger core area where the DC... |
| US-7,046,522 |
Method for scalable architectures in stackable three-dimensional
integrated circuits and electronics The design methods described enable three-dimensional integrated circuit systems in which all of the dies, in a vertically bonded stack of dies, are identical.... |
| US-7,046,521 |
Enclosure with shielded power compartment and methods of shielding
enclosures Apparatus for housing electrically powered components to protect such components from damage and interference caused by lightning strikes and other externally... |
| US-7,046,520 |
Electronic assemblies having supports for circuit boards An electronic assembly apparatus is provided which has a chassis for housing at least one circuit board. The circuit board has at least one major surface. The... |
| US-7,046,519 |
Small card adaptor and host apparatus for insertion of the same A small card adaptor into which a small card is inserted so as to be connected to a personal computer includes a small card identifying portion for identifying... |
| US-7,046,518 |
Power module A power module that houses components of a circuit for driving a three-phase motor. The power module includes a molded shell. A number of leads are embedded... |
| US-7,046,517 |
Electrically isolated semi-locking hinge for cooling system A cooling system hinge mounted to a portion of an enclosure of an electronic system to which a cooling device may be releasably and pivotably attached in at... |
| US-7,046,516 |
Clip for heat sink A clip for heat sink comprises an inverted T-shaped retaining member and an L-shaped operation member pivotably connected to the retaining member. The retaining... |
| US-7,046,515 |
Method and apparatus for cooling a circuit component An apparatus includes a thermally conductive section with a side facing approximately parallel to an axis and adapted to be thermally coupled to a circuit... |
| US-7,046,514 |
Data center cooling A modular data center, for housing and cooling electronic equipment, includes multiple housings, a first portion of the housings configured to hold... |
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