Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,047,465 |
Methods for using defective programmable logic devices by customizing
designs based on recorded defects Methods for utilizing PLDs with localized defects. Each PLD has a unique identifier. In one embodiment, a PLD provider tests a series of PLDs, selecting those... |
| US-7,047,464 |
Method and system for use of a field programmable function within an
application specific integrated circuit... An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell. The standard cell includes a plurality of logic functions. The... |
| US-7,047,463 |
Method and system for automatically determining a testing order when
executing a test flow A method and system for automated multisite testing. Specifically, in one embodiment, a method is disclosed for determining a testing order of plurality of... |
| US-7,047,462 |
Method and apparatus for providing JTAG functionality in a remote server
management controller The disclosed embodiments relate to the field of remote server management. More particularly, the embodiments relate to providing an embedded JTAG master in a... |
| US-7,047,461 |
Semiconductor integrated circuit device with test data output nodes for
parallel test results output A semiconductor integrated circuit device includes test data output nodes arranged in a width of a plurality of bits and an internal data bus, greater in bit... |
| US-7,047,460 |
Method and apparatus for testing a storage interface A tester or method of testing a mass storage interface queues error functions for simulation responsive to condition criteria of such storage simulation. Such... |
| US-7,047,459 |
Method and system for isolation of a fault location in a communications
network The present invention provides system and method of identifying a failure location in any datapath in a set of datapaths in a communication element, each... |
| US-7,047,458 |
Testing methodology and apparatus for interconnects A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This... |
| US-7,047,457 |
Testing of a multi-gigabit transceiver A method for testing a multi-gigabit transceiver begins by configuring the multi-gigabit transceiver for testing. The processing continues by varying a... |
| US-7,047,456 |
Error correction for regional and dynamic factors in communications In an aspect, a method and system is provided to receive and analyze tracked and reported broadcasted data errors, based on a path of the broadcasted data,... |
| US-7,047,455 |
Memory with element redundancy A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one... |
| US-7,047,454 |
Integrated circuit having a data processing unit and a buffer memory An integrated circuit includes a data processing unit, a buffer memory, and a setting memory. The buffer memory performs the function of registers for storing... |
| US-7,047,453 |
Method and apparatus for managing network traffic using cyclical
redundancy check hash functions Methods, apparatus and systems are directed to managing network traffic using a variable length Cyclical Redundancy Check (CRC) index to hash an address header.... |
| US-7,047,452 |
Method and system for detecting excessive use of a data processing system A method (300) for detecting excessive use of a data processing system, such as a computer or a video game, is disclosed. In a first embodiment of the invention,... |
| US-7,047,451 |
Tracing program counter addresses using native program counter format and
instruction count format A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter... |
| US-7,047,450 |
Storage system and a method for diagnosing failure of the storage system A storage system includes at least one storage medium, at least one controller to control the storage medium, and a communication path to connect the storage... |
| US-7,047,449 |
Method for providing cable isolation in a fibre channel test environment
using a software driven PCI device A cable isolator is provided for automatically performing cable breaks for testing of host bus adapters. A workstation includes a host bus adapter, such as a... |
| US-7,047,448 |
Software self-repair toolkit for electronic devices A device and method supporting the identification and correction of firmware and/or software errors is described. Upon the occurrence of a firmware/software... |
| US-7,047,447 |
Method and system for postmortem object type identification A method for postmortem object type identification. In one method embodiment, the present invention accesses a memory dump. Next, a portion of the memory dump is... |
| US-7,047,446 |
Load test system and method An improved system and method for load testing software applications is provided. The user interface and/or application calls are captured to generate a script... |
| US-7,047,445 |
Program starter system, and method of controlling program startup A utility program continuously monitors a data acquisition section into which an auxiliary recording medium is removably inserted, thus detecting an auxiliary... |
| US-7,047,444 |
Address selection for testing of a microprocessor A microprocessor with built-in test, comprising: a register for retaining a test address of a test program; a next address generation logic for generating a... |
| US-7,047,443 |
Microcomputer, electronic equipment and debugging system An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of... |
| US-7,047,442 |
Electronic test program that can distinguish results An electronic test system that distinguishes erroneous and marginal results. The test system includes a memory and an electronic processor for controlling the... |
| US-7,047,441 |
Recovery guarantees for general multi-tier applications A technique is described for guaranteeing recovery in a computer system comprising of recovery contracts with a plurality of obligations for a message exchange... |
| US-7,047,440 |
Dual/triple redundant computer system A dual/triple redundant computer system having in one of the preferred embodiments triple redundant I/O modules and dual redundant central processor modules... |
| US-7,047,439 |
Enhancing reliability and robustness of a cluster A cluster having a host connected thereto via a cluster interconnection fabric where a determination is made as to whether an error condition exists in an I/O... |
| US-7,047,438 |
Accommodation of media defect growth on a data storage medium through
dynamic remapping An apparatus, program product and method of mapping defects on a data storage medium analyze one or more previously-identified defects on a storage medium to... |
| US-7,047,437 |
Method and system for detecting dropped micro-packets A system and a method of providing error detection and correction of transmission of multiple flits between sending and receiving agents connected together in a... |
| US-7,047,436 |
Digital microelectronic circuit with a clocked data-processing unit and a
converting unit A digital microelectronic circuit comprises a clocked data-processing unit (1) and a converting unit (2) which reads in data present at the output of the... |
| US-7,047,435 |
System and method for clock-synchronization in distributed systems A method is provided for synchronizing distributed processors. The method comprises determining a desired number of offset values between two processors, wherein... |
| US-7,047,434 |
Data transfer control device and electronic equipment The objective is to provide a data transfer control device and electronic equipment that make it possible to switch the frequency of a generated clock... |
| US-7,047,433 |
Method and circuit for synchronizing a higher frequency clock and a lower
frequency clock A higher frequency clock and a lower frequency clock are locked at a predetermined phase relationship. A total number of pulses of the higher frequency clock... |
| US-7,047,432 |
Method and system for synchronizing output from differently timed circuits Synchronizing output from timed circuits includes receiving a first clock signal having a first frequency at a first timed circuit. A first sequence of first... |
| US-7,047,431 |
Uninterruptible power supply unit for allowing a computer to wake up
before receiving notification of power failure An uninterruptible power supply unit can communicate with a computer being in a suspend or sleep state. The uninterruptible power supply unit includes a first... |
| US-7,047,430 |
Method for saving chipset power consumption A method of operating a chipset for saving power consumption is provided. Basic operating units, control units and input/output ports are used to simulate the... |
| US-7,047,428 |
Method and apparatus for performing wake on LAN power management A single integrated circuit includes logic that supports 10BASE-T, 100BASE-T and 1000BASE-T transceiver functionality. The invention implements power management... |
| US-7,047,427 |
Disk subsystem A power source control apparatus for a disk subsystem includes a plurality of hard disk drives (HDDs) each with two systems of fiber channel interface ports, an... |
| US-7,047,426 |
Portable computing device communication system and method A method of communicating between a portable computing device and a host computer is provided. The method typically includes storing a responsive action to be... |
| US-7,047,425 |
Scaleable muti-level security method in object oriented open network
systems A system and method are provided for securely transferring data between applications over a network. According to one embodiment, a receive site address on a... |
| US-7,047,424 |
Methods and systems for hairpins in virtual networks Methods and systems are provided for enabling communication between a first processor and a second processor using at least one additional processor separate... |
| US-7,047,423 |
Information security analysis system The analysis system is a collection, configuration and integration of software programs that reside on multiple interconnected computer platforms. The software,... |
| US-7,047,422 |
User access to a unique data subset of a database Described herein is one or more implementations for allowing a user access to a unique data subset of a database. |
| US-7,047,421 |
Data signal with a database and a compressed key Described herein are one or more data signal implementations having at least a database and a compressed key. |
| US-7,047,420 |
Exclusive encryption An exclusive encryption system is established using multiple computing devices. The exclusive encryption system allows for the exclusion of certain plaintext... |
| US-7,047,419 |
Data security system A data security system comprises a host processor, and a plurality of remote computers. Each remote computer provides biometric authentication of a user prior to... |
| US-7,047,418 |
Imaging method and device using biometric information for operator
authentication Essentially coincident with the capture of an image by the imaging device, biometric information indicating the identity of the operator of the device is... |
| US-7,047,417 |
Systems and methods for accessing reporting services An operational support system includes a network interface and a report unit. The network interface receives an identifier and password from a user, determines... |
| US-7,047,416 |
Account-based digital signature (ABDS) system A method of authenticating an entity by a receiving party with respect to an electronic communication that is received by the receiving party and that includes... |
| US-7,047,415 |
System and method for widely witnessed proof of time A system for authenticating records without reliance upon a trusted third party. A first server provides a sequential series of certifications associated with... |
Copyright 2008−2012 Patents.com
