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| Patent # | Description |
|---|---|
| US-7,047,414 |
Managing database for reliably identifying information of device
generating digital signatures A database for reliably identifying a Security Profile of a device that generates digital signatures is managed by (a) maintaining the database in a secure... |
| US-7,047,413 |
Collusion-resistant watermarking and fingerprinting An implementation of a technology is described herein that facilitates rights enforcement of digital goods using watermarks. More particularly, it is a... |
| US-7,047,412 |
Digital watermark data embedding method, and digital watermark data
embeddability analyzing method To lighten the processing load of embedding a digital watermark in content data, a preliminary process (embedding strength map generating process) run by a... |
| US-7,047,411 |
Server for an electronic distribution system and method of operating same A server architecture for a digital rights management system that distributes and protects rights in content. The server architecture includes a retail site... |
| US-7,047,410 |
Digital image watermarking method A digital image watermarking method is provided. The digital image watermarking method includes the steps of combining host image data sets and signature image... |
| US-7,047,409 |
Automated tracking of certificate pedigree A method of automatically tracking a certificate pedigree is provided, in which a new user is provided with a piece of hardware containing a predetermined... |
| US-7,047,408 |
Secure mutual network authentication and key exchange protocol Secure communication protocols are disclosed in which two parties generate a shared secret which may be used as a secure session key for communication between... |
| US-7,047,407 |
Network system enabling transmission control A network system capable of preventing the leakage of a confidential file by an inadvertent act of a transmitting party and capable of meeting the requirement... |
| US-7,047,406 |
Method and system for providing a secure peer-to-peer file delivery
network A method and system for electronically delivering files over a public network is disclosed. The network includes a plurality of computers including at least one... |
| US-7,047,405 |
Method and apparatus for providing secure processing and data storage for
a wireless communication device Techniques for providing secure processing and data storage for a wireless communication device. In one specific design, a remote terminal includes a data... |
| US-7,047,404 |
Method and apparatus for self-authenticating digital records A method for proving the validity of a record digitally signed by a user having a digital certificate issued by a certification authority within a hierarchy of... |
| US-7,047,403 |
Method and system for operating system recovery and method of using
build-to-configuration mode to model... A system for operating system recovery is proposed and includes a data storage device having a first partition, a second partition and a third partition... |
| US-7,047,402 |
Process for booting and causing completion of synchronization based on
multiple actuations of designated key... A Computer based on a dual processing structure, with a main processing subsystem associated to an alternate processing subsystem. The main subsystem includes a... |
| US-7,047,401 |
Handling interrupts during multiple access program instructions A data processing apparatus 2 supports multiple memory access program instructions LDM, STM which serve to load data values from multiple program registers 16 to... |
| US-7,047,400 |
Single array banked branch target buffer An Instruction Pointer (IP) signal is received comprising an IP tag field and an IP set field. A plurality of entries corresponding to the IP set field are read,... |
| US-7,047,399 |
Computer system and method for fetching, decoding and executing
instructions A computer system for executing branch instructions and a method of executing branch instructions are described. Two instruction fetchers respectively fetch a... |
| US-7,047,398 |
Analyzing instruction completion delays in a processor A method and system for identifying instruction completion delays for a group of instructions in a computer processor. Each instruction in the group of... |
| US-7,047,397 |
Method and apparatus to execute an instruction with a semi-fast operation
in a staggered ALU A method for executing an instruction with a semi-fast operation in a staggered ALU. The method of one embodiment comprises generating a first operation and a... |
| US-7,047,396 |
Fixed length memory to memory arithmetic and architecture for a
communications embedded processor system A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for... |
| US-7,047,395 |
Reordering serial data in a system with parallel processing flows A distributed system is provided for apportioning an instruction stream into multiple segments for processing in multiple parallel processing units, and for... |
| US-7,047,394 |
Computer for execution of RISC and CISC instruction sets A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction... |
| US-7,047,393 |
Coprocessor processing instruction with coprocessor ID to broadcast main
processor register data element to... A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing... |
| US-7,047,392 |
Data processing apparatus and method for controlling staged multi-pipeline
processing A data processing apparatus that reduces a fanout load of a control signal for controlling a pipeline includes a first pipeline processing portion for executing... |
| US-7,047,391 |
System and method for re-ordering memory references for access to memory A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer... |
| US-7,047,390 |
Method, system, and program for managing a relationship between one target
volume and one source volume Provided are a method, system, and program for managing a relationship between one target volume and one source volume. For each of the source volume and target... |
| US-7,047,389 |
Memory allocation method and computer readable medium The present invention provides a memory allocation method and the like, meaning that user usability and the level of service for the user can be improved. The... |
| US-7,047,388 |
Control method for storage device controller system, and storage device
controller system The present invention provides a control method for a storage device controller system provided with a first storage device controller that is connected to first... |
| US-7,047,387 |
Block cache size management via virtual memory manager feedback A method for calculating a block cache size for a host process or application on a computer based at least upon virtual memory page evictions and/or virtual... |
| US-7,047,386 |
Dynamic partitioning of a reusable resource Techniques for managing changes in a computer system include storing, in a storage space, undo information for removing changes that are being made by entities.... |
| US-7,047,385 |
High-speed memory for use in networking systems A memory integrated circuit includes an array of high-speed memory blocks coupled to the address input interface and data output interface of the integrated... |
| US-7,047,384 |
Method and apparatus for dynamic timing of memory interface signals A method and apparatus for using different timings to latch signals sent by two memory devices of identical design to compensate for differences in the lengths... |
| US-7,047,383 |
Byte swap operation for a 64 bit operand A method for a byte swap operation on a 64 bit operand. The method of one embodiment comprises accessing an operand stored in a register. The operand is... |
| US-7,047,382 |
System and method for managing compression and decompression and
decompression of system memory in a computer... A method and system for allowing a processor or I/O master to address more system memory than physically exists are described. A Compressed Memory Management... |
| US-7,047,381 |
System and method for providing one-time programmable memory with fault
tolerance Systems and methods that provide a one-time programmable (OTP) memory with fault tolerance are provided. In one example, the OTM memory may include a data... |
| US-7,047,380 |
System and method for using file system snapshots for online data backup A system for data backup includes a storage device, a backup storage device, and an intermediate storage device. Backup procedure is performed on-line and copies... |
| US-7,047,379 |
Autonomic link optimization through elimination of unnecessary transfers Disclosed are a system, a method, and a computer program product to efficiently create consistent transaction sets to maintain one or more copies of data at... |
| US-7,047,378 |
Method, system, and program for managing information on relationships
between target volumes and source volumes... Provided are a method, system, and program for managing a relationship between one target volume and one source volume. Information is maintained in memory on an... |
| US-7,047,377 |
System and method for conducting an auction-based ranking of search
results on a computer network A flexible data transfer and data synchronization system is described. Local and geographically remote systems comprise a data processing network. Each remote... |
| US-7,047,376 |
Backup system and method and program A remote site stores data received from a currently-used site and transfers the stored data to a proximal site. The proximal site stores the data received from... |
| US-7,047,375 |
Memory system and method for two step memory write operations A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a... |
| US-7,047,374 |
Memory read/write reordering Memory bandwidth may be enhanced by reordering read and write requests to memory. A read queue can hold multiple read requests and a write queue can hold... |
| US-7,047,373 |
Memory control apparatus and method for controlling memory access capable
of selecting desirable page mode In a memory control apparatus and a method for controlling memory access capable of selecting a desirable page mode, so as to reduce memory access time, a... |
| US-7,047,372 |
Managing I/O accesses in multiprocessor systems A computer system is described having a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory including a... |
| US-7,047,371 |
Integrated memory having a memory cell array containing a plurality of
memory banks, and circuit configuration... An integrated memory has at least two connection panels, which can be operated independently of one another, for external communication by the memory. In... |
| US-7,047,370 |
Full access to memory interfaces via remote request A technique for enabling a processor to access a memory not directly coupled to the processor. According to the technique, a local processor accesses a remote... |
| US-7,047,369 |
Software application environment The invention contains an application operating environment in which acceptable and/or suspect activities may be defined for an application so that unacceptable... |
| US-7,047,368 |
Memory reallocation and sharing in electronic systems Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a... |
| US-7,047,367 |
Information processing device and setting method for same An information processing device is provided which is capable of automatically initializing external apparatuses, when external apparatuses are connected... |
| US-7,047,366 |
QOS feature knobs Described are various quality of service (QOS) parameters that may be used in characterizing device behavior in connection with a cache. A Partition parameter... |
| US-7,047,365 |
Cache line purge and update instruction A method and apparatus for purging a cache line from an issuing processor and sending the cache line to the cache of one or more processors in a multi-processor... |
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