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| Patent # | Description |
|---|---|
| US-7,054,224 |
Non-synchronous semiconductor memory device having page mode read/write The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew... |
| US-7,054,223 |
Semiconductor memory device A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line... |
| US-7,054,222 |
Write address synchronization useful for a DDR prefetch SDRAM Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The... |
| US-7,054,221 |
Data pass control device for masking write ringing in DDR SDRAM and method
thereof The present invention relates to a data pass control device for masking a ringing of a data strobe that occurs when a write operation in a DDR SDRAM is... |
| US-7,054,220 |
Memory device having repeaters Disclosed is a memory device having repeaters capable of preventing an expected signal delay and a signal distortion caused by a long transmission length of a... |
| US-7,054,219 |
Transistor layout configuration for tight-pitched memory array lines A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array... |
| US-7,054,218 |
Serial memory address decoding scheme A decode circuit for a memory that uses "sequential addressing" includes a series of decoders form a shift register that may be used to provide either wordlines... |
| US-7,054,217 |
Semiconductor memory device A semiconductor memory device capable of improving the operating speed while suppressing size increase is provided. This semiconductor device comprises a... |
| US-7,054,216 |
Programmable MOS device formed by hot carrier effect A programmable metal-oxide-semiconductor (MOS) memory circuit and the method for programming same and disclosed. The circuit comprises a first N-type transistor... |
| US-7,054,215 |
Multistage parallel-to-serial conversion of read data in memories, with
the first serial bit skipping at least... Data bits are prefetched from memory cells in parallel and are read out serially. The memory includes multiple stages (1710) of latches through which the... |
| US-7,054,214 |
Semiconductor device A dummy cell includes a plurality of first memory cells MC for storing "1" or "0", arranged at points of intersection between a plurality of word lines WR0 to... |
| US-7,054,213 |
Method and circuit for determining sense amplifier sensitivity A dynamic random access memory (DRAM) includes a bit line pair, including a first bit line and a second bit line. Memory cells and a sense amplifier are coupled... |
| US-7,054,212 |
Sense amplifier with adaptive reference generation A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a... |
| US-7,054,211 |
Semiconductor memory storage device capable of high operating speed A semiconductor memory storage is disclosed, in which the gate of each of a plurality of n-channel transistors is connected to the corresponding one of a... |
| US-7,054,210 |
Write/precharge flag signal generation circuit and circuit for driving bit
line isolation circuit in sense... Provided is a bitline isolation circuit in a sense amplifier generating an isolation signal for controlling an isolation circuit to isolate a connection between... |
| US-7,054,209 |
Semiconductor memory device and test method thereof A semiconductor memory device vice disclosed herein comprises: a memory cell array divided into a plurality of blocks, each of which includes a plurality of... |
| US-7,054,208 |
Method and device for testing a sense amp As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory... |
| US-7,054,207 |
Method and system for selecting redundant rows and columns of memory cells A system and method for selecting redundant rows and columns of memory devices includes a column select steering circuit to couple column select signals from a... |
| US-7,054,206 |
Sub-column-repair-circuit An arrangement for repairing at least one faulty bit line of a memory includes three multiplexer stages. The memory has a plurality of columns, each column... |
| US-7,054,205 |
Circuit and method for determining integrated circuit propagation delay A circuit and method is provided for determining the delay of an integrated circuit common associated with chip-to-chip variations in the manufacturing process,... |
| US-7,054,204 |
Semiconductor device and method for controlling the same Disclosed herein are a semiconductor method and device which are capable of reducing data write errors by rewriting last write data during a write recovery time... |
| US-7,054,203 |
High reliability memory element with improved delay time In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Two settable memory elements, and a... |
| US-7,054,202 |
High burst rate write data paths for integrated circuit memory devices and
methods of operating same Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to... |
| US-7,054,201 |
Driving circuit for non-volatile DRAM A driving circuit for use in a non-volatile dynamic random access memory (NVDRAM) having a nonconductor which can trap electrons or holes includes an internal... |
| US-7,054,200 |
Semiconductor device A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is... |
| US-7,054,199 |
Multi level flash memory device and program method We describe a multi level flash memory device and program method. The multi level flash memory device includes a plurality of memory cells, each storing an... |
| US-7,054,198 |
Flash memory with fast boot block access A flash memory device and system include a boot block voltage pump for providing a word line voltage to the boot block of the flash memory. At least one... |
| US-7,054,197 |
Method for reading a nonvolatile memory device and nonvolatile memory
device implementing the reading method A reading method for a nonvolatile memory device, wherein the gate terminals of the array memory cell and of the reference memory cell are supplied with a same... |
| US-7,054,196 |
Method for programming P-channel EEPROM A method for programming a P-channel EEPROM having an N-well, a floating gate, a control gate, a P-type source region and a P-type drain region is provided. In... |
| US-7,054,195 |
Nonvolatile semiconductor memory The number of electrons existing in a channel region within a NAND cell unit is reduced, and erroneous write-in characteristics are improved by the present... |
| US-7,054,194 |
Non-volatile SRAM cell having split-gate transistors This specification discloses a non-volatile static random access memory (SRAM) cell with the feature of keeping data even after the power is turned off. It... |
| US-7,054,193 |
Non-uniform programming pulse width for writing of multi-bit-per-cell
memories Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming... |
| US-7,054,192 |
Method of controlling threshold voltage of NROM cell A method of two-sided asymmetric programming with a one-sided read for a Nitride Read Only Memory (NROM) cell with different quantity of stored charges uses the... |
| US-7,054,191 |
Method and system for writing data to memory cells A first and a second set of memory cells are connected to the same first word line and second word line. At the commencement of data writing, the first word line... |
| US-7,054,190 |
Logic-in-memory circuit using magnetoresistive element A TMR network 120 using TMR elements as magnetoresistive elements is formed as a variable resistive element network by a series-parallel connection of two kinds... |
| US-7,054,189 |
Magnetic random access memory Blocks are connected to a read bit line. One block has MTJ elements which are connected to each other in series between the read bit line and a ground terminal.... |
| US-7,054,188 |
Magnetic memory device A magnetic memory device includes a memory cell array including MTJ elements provided at the coordinates (x, y). First write lines extend in a direction neither... |
| US-7,054,187 |
Magnetic memory A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first writing wiring extending in a first direction on or... |
| US-7,054,186 |
Magnetic random access memory There is disclosed a magnetic random access memory according to an example of the present invention, comprising first and second write lines which intersect with... |
| US-7,054,185 |
Optimized MRAM current sources A word current source (445) for a magnetoresistive random access memory circuit (420) includes an n-channel transistor (430) including a gate, a source and a... |
| US-7,054,184 |
Cache late select circuit A late select circuit topology has pseudo-static circuits that provide fast dynamic circuit operation without the use of dynamic clock timing signals. An output... |
| US-7,054,183 |
Adaptive programming technique for a re-writable conductive memory device A programming circuit is provided. As a conductive memory cell is programmed, its resistance changes. The provided programming circuit monitors the changing... |
| US-7,054,182 |
Nonvolatile FeRam control device Disclosed is a nonvolatile ferroelectric FeRAM control device which allows a programmable register to be stably driven in a low voltage region by controlling a... |
| US-7,054,181 |
Non-volatile ferroelectric cell array block having hierarchy transfer
sensing architecture The present invention discloses a non-volatile ferroelectric cell array block having a hierarchy transfer sensing architecture. The cell array block of the... |
| US-7,054,180 |
Method and circuit for adjusting a resistance in an integrated circuit A method for adjusting a resistance in an integrated circuit, the resistance having a first conductive area and a second conductive area between which a... |
| US-7,054,179 |
Double-high memory system compatible with termination schemes for
single-high memory systems A double-high memory system compatible with termination schemes for single-high memory systems. The system includes an interface for input and output of data. A... |
| US-7,054,178 |
Datapath architecture for high area efficiency A particular DRAM data path architecture is disclosed. In accordance with this invention, the sharing of MDQ sense amplifiers simplifies the circuit design of... |
| US-7,054,177 |
Power adapter The present invention provides a power adapter which includes a power input connector, a voltage transfer and a power output connector. The power input and... |
| US-7,054,176 |
Architecture for achieving resonant circuit synchronization of multiple
zero voltage switched push-pull DC-AC... A multi-stage, push-pull driven, resonant DC-AC converter ties the center-taps of primary windings of respective push-pull stages together, and drives each... |
| US-7,054,175 |
DC-DC converter A circuit configuration in which a pair of conversion circuit parts for converting a power source voltage of a DC power source into an AC by two pairs of... |
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