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| Patent # | Description |
|---|---|
| US-7,055,025 |
System and method for boot mode control A system for boot mode control using analysis of power state and system mode. The system includes an input unit, a system power state pin, and a keyboard... |
| US-7,055,024 |
Computer system component initialization using a BIOS formal hardware
language to represent the initialization... A BIOS system and method to initialize the platform hardware components of a computer system. An object oriented abstraction of each hardware component, the... |
| US-7,055,023 |
Apparatus and method for branch prediction where data for predictions is
selected from a count in a branch... An apparatus for branch prediction includes a history register which stores therein history of previous branch instructions, an index generation circuit which... |
| US-7,055,022 |
Paired load-branch operation for indirect near jumps A microprocessor apparatus is provided for performing an indirect near jump operation that includes paired operation translation logic, load logic, and execution... |
| US-7,055,021 |
Out-of-order processor that reduces mis-speculation using a replay
scoreboard A pipelined processor includes a dependency scoreboard that tracks dependency for replay of instructions capable of executing out-of-order. Early instructions... |
| US-7,055,020 |
Flushable free register list having selected pointers moving in unison A method and apparatus is provided for restoring a free physical register list to its previous state without having to physically restore any data. The method... |
| US-7,055,019 |
Matched instruction set processor systems and method, system, and
apparatus to efficiently design and implement... This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction... |
| US-7,055,018 |
Apparatus for parallel vector table look-up Methods and apparatuses for performing simultaneous table look-up using multiple look-up tables. In one aspect of the invention, an execution unit in a... |
| US-7,055,017 |
Optical disk drive, method for formatting optical disk, and optical disk An optical disk drive for initializing an optical disk by dividing a recording area into zones and by assigning logical addresses to each of the zones. The disk... |
| US-7,055,016 |
Computer system including a memory controller configured to perform
pre-fetch operations A computer system including a memory controller configured to perform pre-fetch operations. A computer system includes a first system memory, a second system... |
| US-7,055,015 |
Information processing apparatus in which processes can reduce overhead of
memory access and efficiently share... The information processing apparatus reserves a direct mapping region in the physical memory space and correlates physical addresses of the direct mapping region... |
| US-7,055,014 |
User interface system for a multi-protocol storage appliance A user interface system that simplifies management of a storage system, such as a multi-protocol storage appliance, by a user or system administrator. The user... |
| US-7,055,013 |
Spare data site allocation A method of allocating data sites of a storage device based on quality of the data sites, according to a particular embodiment of the invention, includes... |
| US-7,055,012 |
Latency reduction using negative clock edge and read flags A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because... |
| US-7,055,011 |
Remote copy network A remote copy network realizes low-cost multi-hop remote copying. Remote copying is executed via a remote copy network (RCN) having a source edge device... |
| US-7,055,010 |
Snapshot facility allowing preservation of chronological views on block
drives A method for efficiently maintaining snapshot instances. To maintain the state of snapshot instances, the snapshot copies the data needed to be protected into... |
| US-7,055,009 |
Method, system, and program for establishing and maintaining a
point-in-time copy Provided are a method, system, and program for establishing a point-in-time copy. Input/Output (I/O) requests to tracks identified as source tracks and... |
| US-7,055,008 |
System and method for backing up data A hash-optimized backup system and method takes data blocks and generates a probabilistically unique digital fingerprint of the content of each data block using... |
| US-7,055,007 |
Data processor memory circuit A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first... |
| US-7,055,006 |
System and method for blocking cache use during debugging A system includes at least one memory operable to store a first flag identifying whether a cache is disabled and a second flag identifying whether use of the... |
| US-7,055,005 |
Methods and apparatus used to retrieve data from memory into a RAM
controller before such data is requested A memory controller retrieves data from memory before such data has actually been requested by an electrical device. The RAM controller may store such data into... |
| US-7,055,004 |
Pseudo-LRU for a locking cache The present invention provides for a cache-accessing system employing a binary tree with decision nodes. A cache comprising a plurality of sets is provided. A... |
| US-7,055,003 |
Data cache scrub mechanism for large L2/L3 data cache structures A method of reducing errors in a cache memory of a computer system (e.g., an L2 cache) by periodically issuing a series of purge commands to the L2 cache,... |
| US-7,055,002 |
Integrated purge store mechanism to flush L2/L3 cache structure for
improved reliabity and serviceability A method of reducing errors in a cache memory of a computer system (e.g., an L2 cache) by periodically issuing a series of purge commands to the L2 cache,... |
| US-7,055,001 |
Storage array controller with a nonvolatile memory as a cache memory and
control method of the same To receive a data input/output request from an information processor and writing data in a hard disk drive in accordance with the data input/output request, a... |
| US-7,055,000 |
Disk drive employing enhanced instruction cache management to facilitate
non-sequential immediate operands A disk drive is disclosed for executing a program comprising a plurality of instructions. The disk drive comprises a primary memory for storing the instructions,... |
| US-7,054,999 |
High speed DRAM cache architecture A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit... |
| US-7,054,998 |
File mode RAID subsystem A method and system enables data redundancy across servers, networks, and controllers by using standard redundant files as underlying storage for RAID subsystem... |
| US-7,054,997 |
Disk array system and cache control method Disclosed is a disk array system that can be expanded effectively in scale by increasing the number of input/output channels and disk adapters and improved in... |
| US-7,054,996 |
Method and device for storing and matching arbitrary wide expressions to
content addressable memories The present invention relates to a method for storing arbitrarily wide expressions (31) in a set of Content Addressable Memory (CAMs) elements (33) where each... |
| US-7,054,995 |
Dynamic linking of banks in configurable content addressable memory
systems A content addressable memory (CAM) system includes CAM banks that can be linked together in a series to form a CAM module. Each CAM bank includes a CAM array... |
| US-7,054,994 |
Multiple-RAM CAM device and method therefor A method and system for storing arranged data in a memory, the system including: (a) a plurality of random access memories, each random access memory (RAM) of... |
| US-7,054,993 |
Ternary content addressable memory device A ternary content addressable memory device. The device includes a ternary CAM array segmented into a plurality of array groups, each of which includes a number... |
| US-7,054,992 |
Synchronous flash memory with non-volatile mode register A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The... |
| US-7,054,991 |
Method for controlling non-volatile semiconductor memory system In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium... |
| US-7,054,990 |
External storage device using non-volatile semiconductor memory The external storage device according to the present invention which uses a non-volatile semiconductor memory such as a flash memory is provided with plural... |
| US-7,054,989 |
Stream processor The stream processor of the present invention includes: a selection section and first to fifth processing sections. In the selection section, a plurality of... |
| US-7,054,988 |
Bus interface for processor The present invention may generally provide a processor circuit comprising a processor, a first bus, a bus pipeline stage, and a second bus. The first bus may be... |
| US-7,054,987 |
Apparatus, system, and method for avoiding data writes that stall
transactions in a bus interface A bus interface unit is adapted to receive transaction requests for at least two different targets. The bus interface unit monitors a capacity of a resource... |
| US-7,054,986 |
Programmable CPU/interface buffer structure using dual port RAM Disclosed is a programmable buffer circuit (16) for interfacing a CPU (12) to a plurality of channel interfaces (14). The buffer circuit includes a dual port... |
| US-7,054,985 |
Multiple hardware partitions under one input/output hub A method and a mechanism are capable of partitioning computer hardware components or elements at the level of individual processing paths, or ropes. Incoming and... |
| US-7,054,984 |
Structure and method for extended bus and bridge in the extended bus A structure and a method for an extended bus and a bridge in the extended bus are disclosed. The structure of the extended bus has a first accelerated graphics... |
| US-7,054,983 |
USB-HUB device and its control method A USB-HUB device in which a request for a device connected to a port of the USB-HUB device may be executed by commonly using a serial interface engine of the HUB... |
| US-7,054,982 |
Fieldbus interface board An apparatus and method including a fieldbus interface board connected to a fieldbus line. The fieldbus interface board includes a main control unit controlling... |
| US-7,054,981 |
Methods and apparatus for providing automatic high speed data connection
in portable device In a portable FireWire compatible device, a direct memory access (DMA) bus switch coupled by way of a DMA bus to a central processing unit (CPU), a local hard... |
| US-7,054,980 |
Multiple drive controller A drive controller for controlling multiple disk drives is disclosed. In one embodiment, the drive controller includes a physical interface circuit configured... |
| US-7,054,979 |
Method and apparatus for routing configuration accesses from a primary
port to a plurality of secondary ports The method of routing configuration accesses applied from the primary port to a plurality of secondary ports includes the steps of: distributing a plurality of... |
| US-7,054,978 |
Logical PCI bus A method of and apparatus for improving the efficiency of a data processing system employing multiple busses operating at multiple data transfer rates. Each of... |
| US-7,054,977 |
Method of handling data in a network device A network device for handling data and a method for handling data in a network device are disclosed. The network device includes at least one media port and at... |
| US-7,054,976 |
Computer system having improved interface A computer system includes a computer body and a main board installed in the computer body, the main board having a digital controller configured to support an... |
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