Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,193,915 |
Semiconductor memory device When a command is input to a semiconductor memory device, a sub-threshold current is reduced to a predetermined value corresponding to the command. After the... |
| US-7,193,914 |
Open digit line array architecture for a memory array A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and... |
| US-7,193,913 |
Sense amplifier circuit and read/write method for semiconductor memory
device A sense amplifier circuit comprising a local I/O line pair, a global I/O line pair, a write amplification unit for amplifying and transferring data output from... |
| US-7,193,912 |
Semiconductor integrated circuit device A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of... |
| US-7,193,911 |
Page buffer for preventing program fail in check board program of
non-volatile memory device A page buffer in which the value of data that have been latched in a register of a page buffer is not changed by slowly transmitting data to the register in a... |
| US-7,193,910 |
Adjustable timing circuit of an integrated circuit An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the... |
| US-7,193,909 |
Signal processing circuits and methods, and memory systems A signal processing circuit. A first flip flop samples a reference signal by rising edges of the data strobe signal, and outputs a first sampling signal. A... |
| US-7,193,908 |
Semiconductor memory Provided is a semiconductor memory, comprising: a voltage converting circuit which voltage-converts a resistance difference between a first and a second... |
| US-7,193,907 |
Semiconductor integrated circuit having a power-on reset circuit in a
semiconductor memory device A semiconductor integrated circuit, which operates in accordance with a power supply voltage and an external clock signal and includes a memory circuit, includes... |
| US-7,193,906 |
Voltage regulating circuit and method of regulating voltage Provided is concerned with a voltage regulation circuit and method of regulating the voltage, including a reference voltage generator for generating a reference... |
| US-7,193,905 |
RRAM flipflop rcell memory generator An RRAM flip-flop rcell memory of the type having a write address decoder, a read address decoder, a set of n flip flops, one AND gate associated with each flip... |
| US-7,193,904 |
Random access memory with stability enhancement and early read elimination A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to... |
| US-7,193,903 |
Method of controlling an integrated circuit capable of simultaneously
performing a data read operation and a... A method of controlling an integrated circuit (IC) capable of simultaneously performing a data read operation and a data write operation is provided. The method... |
| US-7,193,902 |
Method of erasing a flash memory cell Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate... |
| US-7,193,901 |
Monitoring the threshold voltage of frequently read cells A canary cell may be used in a semiconductor memory to indicate an incipient failure. For example, the canary cell may be provided on rows in a flash memory.... |
| US-7,193,900 |
CACT-TG (CATT) low voltage NVM cells Described herein are the methods the CACT and TG Non-volatile program erase methods, for programming and erasing NVM cells. This combination allows use of low... |
| US-7,193,899 |
Erase block data splitting A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data... |
| US-7,193,898 |
Compensation currents in non-volatile memory read operations Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge... |
| US-7,193,897 |
NAND flash memory device capable of changing a block size Disclosed herein is a NAND flash memory device capable of changing a block size. In NAND flash memory devices capable of changing a block size, each memory block... |
| US-7,193,896 |
Multi-value semiconductor memory device and method capable of caching a
lower page data upon an incomplete... A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged to store multi-value... |
| US-7,193,895 |
Redundant memory content substitution apparatus and method A memory apparatus includes a main memory, a redundant memory, and a substitution control unit. The main memory is configured to receive a read address and... |
| US-7,193,894 |
Clock synchronized nonvolatile memory device A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural... |
| US-7,193,893 |
Write once read only memory employing floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate... |
| US-7,193,892 |
Magnetic switching with expanded hard-axis magnetization volume at
magnetoresistive bit ends A magnetoresistive apparatus and method of operation with improved switching characteristics is provided. Switching of a magnetic direction of a magnetic layer... |
| US-7,193,891 |
Spin based sensor device A spin based electronic device can be used as a magnetic field sensor. The device uses ferromagnetic materials for implementing a variable spin resistance. An... |
| US-7,193,890 |
Magnetoresistive effect device, magnetic random access memory, and
magnetoresistive effect device manufacturing... A magnetoresistive effect device includes a first ferromagnetic layer having a fixed magnetization direction and having magnetic moment ml per unit area. A... |
| US-7,193,889 |
Switching of MRAM devices having soft magnetic reference layers A magnetic random access memory (MRAM) that includes an array of magnetic memory cells and a plurality of word and bit lines connecting columns and rows of the... |
| US-7,193,888 |
Nonvolatile memory circuit based on change in MIS transistor
characteristics A memory circuit includes a latch having a first node and a second node, a plate line, a word selecting line, a first MIS transistor having source/drain nodes... |
| US-7,193,887 |
SRAM circuitry A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that... |
| US-7,193,886 |
Integrated circuit with a memory of reduced consumption An integrated circuit comprising volatile memory elements, interface circuits connected to the volatile memory elements and, possibly, logic circuits not... |
| US-7,193,885 |
Radiation tolerant SRAM bit In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter... |
| US-7,193,884 |
Semiconductor memory device A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold... |
| US-7,193,883 |
Input return path based on V.sub.ddq/V.sub.ssq Input circuit configurations that reduce the amount of input signal jitter caused by a common input signal return path, methods and circuits utilizing the same... |
| US-7,193,882 |
Semiconductor memory device To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a... |
| US-7,193,881 |
Cross-point ferroelectric memory that reduces the effects of bit line to
word line shorts A memory constructed from a dielectric layer sandwiched between a plurality of word conductors and a plurality of bit line conductors is disclosed. The... |
| US-7,193,880 |
Plateline voltage pulsing to reduce storage node disturbance in
ferroelectric memory Methods (50, 70) and ferroelectric devices (102) are presented, in which pulses (113) are selectively applied to platelines (PL) of one or more non-selected... |
| US-7,193,879 |
Techniques for multiple frequency chirp readout of material with
inhomogeneously broadened absorption spectrum Techniques for reading the spectral content of a spatial-spectral grating in an inhomogeneously broadened transition (IBT) material include directing multiple... |
| US-7,193,878 |
Semiconductor memory device layout including increased length connection
lines An integrated circuit memory device includes a memory cell array including first and second bit lines that extend side-by-side, a plurality of page buffers, a... |
| US-7,193,877 |
Content addressable memory with reduced test time A CAM device having internal circuitry to reduce test time through parallel test setup and parallel pass/fail result generation. A plurality of match results is... |
| US-7,193,876 |
Content addressable memory (CAM) arrays having memory cells therein with
different susceptibilities to soft errors A CAM array has at least one row therein containing a plurality of memory cells with different susceptibilities to soft errors. The memory cells having reduced... |
| US-7,193,875 |
Cache hit logic of cache memory A cache hit logic for determining whether data required by a processor is stored in a cache memory includes a dummy cell string that operates the same as a sense... |
| US-7,193,874 |
Content addressable memory device A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a... |
| US-7,193,873 |
Cradle for receiving an adapter A cradle casing has a DC/DC adapter to receive DC power from a DC power source and generate a first DC power signal. A sleeve accepts an AC/DC adapter, and... |
| US-7,193,872 |
Solar array inverter with maximum power tracking An inverter for use in connecting a DC power source to the utility grid includes a single DC-DC conversion stage, maximum (source) power tracking, and current... |
| US-7,193,871 |
DC-DC converter circuit Provided is a DC-DC converter circuit which is stably operated without being affected by a size of an output capacitor (111) and a cost thereof. When a switching... |
| US-7,193,870 |
Method and apparatus for dissipative clamping of an electrical circuit Dissipative clamping apparatuses and methods for electrical circuits. In one aspect of the invention, In one aspect of the invention, a method includes switching... |
| US-7,193,869 |
Noise suppressor A noise suppressor capable of achieving reduction in size and weight of devices is provided. The noise suppressor is a circuit for suppressing normal mode noise... |
| US-7,193,868 |
Switching power supply circuit A wide-range compatible voltage resonant converter provides high efficiency and allows use of low-breakdown-voltage products for a circuit. The voltage resonant... |
| US-7,193,867 |
DC converter A DC converter alternately turns on and off a main switch Q1 connected in series with a primary winding P1 of a transformer T and a sub-switch Q2 contained in a... |
| US-7,193,866 |
Half-bridge LLC resonant converter with a synchronous rectification
function The invention discloses a half-bridge LLC resonant converter with a synchronous rectification function that includes a first switch; a second switch; a first... |
Copyright 2008−2012 Patents.com
