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| Patent # | Description |
|---|---|
| US-7,194,619 |
Remotely booting devices in a dense server environment without manually
installing authentication parameters on... A method, system and computer program product for remotely booting devices. A deployment server may remotely transmit authentication parameter(s), e.g., public... |
| US-7,194,618 |
Encryption and authentication systems and methods In a disclosed method for authenticating a digital signature key, a record is prepared that includes an integrated combination of indicia uniquely corresponding... |
| US-7,194,617 |
Method and apparatus to prevent the unauthorized copying of digital
information A method for authorizing the rendering of a digital recording. A first section and a last section of a track is first identified. A watermark is then decoded... |
| US-7,194,616 |
Flexible temporary capacity upgrade/downgrade in a computer system without
involvement of the operating system According to the present invention a method and a device is provided for concurrent removal of processor capacity from a running computer. The method and device... |
| US-7,194,615 |
Reconfigurable apparatus being configurable to operate in a logarithmic
scale An integrated circuit has a command/control bus and a number of processing elements. The processing elements contain a number of parts, each part being connected... |
| US-7,194,614 |
Boot swap method for multiple processor computer systems A boot swap method for multiple processor computer systems utilizes a baseboard management controller (BMC) to manage the abnormal booting problem of multiple... |
| US-7,194,613 |
Communication protocol for serial peripheral devices A computing system comprising a host device which includes a serial communication bus and a processor for controlling communication over the serial communication... |
| US-7,194,612 |
System and method to export pre-boot system access data to be used during
operating system runtime A system and method for sharing pre-boot data with agents in the operating system (OS) runtime is disclosed. The disclosed system and method provides a means by... |
| US-7,194,611 |
Method and system for navigation using media transport controls A system and method for improved navigation and access of computer media content using media transport controls is provided. These transport controls may be... |
| US-7,194,610 |
Processor and pipeline reconfiguration control method A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a... |
| US-7,194,609 |
Branch reconfigurable systems and methods The invention is a system and method for executing programs. The invention involves a plurality of processing elements, wherein a processing element of the... |
| US-7,194,608 |
Method, apparatus and computer program product for identifying sources of
performance events Event vectors are included in an instruction tracking structure of a processor to collect history for every instruction flowing through the processor. Such an... |
| US-7,194,607 |
Method and apparatus for command translation and enforcement of ordering
of commands An adaptive arrangement including a command translation/ordering unit arranged to recognize and convert a first predetermined command unrecognizable/unsupported... |
| US-7,194,606 |
Method and apparatus for using predicates in a processing device A method of controlling an operation of a processing device that comprises at least a first and second predicate execution registers comprises predicating a... |
| US-7,194,605 |
Cache for instruction set architecture using indexes to achieve
compression A method for compressing a set of instructions in an adaptive computing machine includes identifying frequently executed instructions, inserting an explicit... |
| US-7,194,604 |
Address generation interlock resolution under runahead execution Disclosed is a method and apparatus providing a microprocessor the ability to reuse data cache content fetched during runahead execution. Said data is stored and... |
| US-7,194,603 |
SMT flush arbitration A methodology to process flushes in an SMT processor with a dynamically shared group completion table (GCT) and a Flush table comprises identification of... |
| US-7,194,602 |
Data processor A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines... |
| US-7,194,601 |
Low-power decode circuitry and method for a processor having multiple
decoders A processor includes first decoder logic capable of decoding a plurality of encoded instructions comprising a first instruction set, the first decoder logic... |
| US-7,194,600 |
Method and apparatus for processing data with a programmable gate array
using fixed and programmable processors A method and apparatus for processing data within a programmable gate array comprise a first fixed logic processor and a second fixed logic processor that are... |
| US-7,194,599 |
Configurable co-processor interface A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer... |
| US-7,194,598 |
System and method using embedded microprocessor as a node in an adaptable
computing machine The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes,... |
| US-7,194,597 |
Method and apparatus for sharing TLB entries A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example... |
| US-7,194,596 |
Method of efficient data management with flash storage system A data management for a flash memory device is disclosed. The device includes a screen virtual sector table and a virtual unit versus physical unit table (V2P... |
| US-7,194,595 |
Technique for translating a hybrid virtual volume file system into a pure
virtual file system data stream A technique translates a hybrid virtual volume (vvol) having a file system that contains intermingled virtual and physical volume block numbers (vbns) into a... |
| US-7,194,594 |
Storage area management method and system for assigning physical storage
areas to multiple application programs Provided are an area management table, an operation management policy, and a resource broker. In the area management table, one or more physical area IDs for... |
| US-7,194,593 |
Memory hub with integrated non-volatile memory A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for... |
| US-7,194,592 |
Storage system using load balancing among systems of varying performance According to this invention, in an environment in which are intermixed a plurality of storage subsystems with different processing performance, volumes are... |
| US-7,194,591 |
Data communication apparatus and method for managing memory in the same A plurality of services are defined for one service memory field (overlap service), and a plurality of access methods, such as "only read" and "read/write", are... |
| US-7,194,590 |
Three data center adaptive remote copy A storage apparatus configuration in a three data center architecture comprises first and second data storage systems, and a remote data storage system. The... |
| US-7,194,589 |
Reducing disk IO by full-cache write-merging An electronic and computerized system that coalesces write operations using a buffer cache which stores data waiting to be written back to a disk of the... |
| US-7,194,588 |
Method for reproducing digital information and digital information
recording or reproducing device A method for reproducing digital information includes the steps of: transferring, with a control circuit, information in a hard disk drive to a memory... |
| US-7,194,587 |
Localized cache block flush instruction A microprocessor and a related compiler support a local cache block flush instruction in which an execution unit of a processor determines an effective address.... |
| US-7,194,586 |
Method and apparatus for implementing cache state as history of read/write
shared data A method and apparatus are provided for implementing a cache state as history of read/write shared data for a cache in a shared memory multiple processor... |
| US-7,194,585 |
Coherency controller management of transactions The management of transactions received by a coherency controller is disclosed. A method of an embodiment of the invention is performed by a coherency controller... |
| US-7,194,583 |
Controlling the replacement of prefetched descriptors in a cache A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor... |
| US-7,194,582 |
Microprocessor with improved data stream prefetching A microprocessor with multiple stream prefetch engines each executing a stream prefetch instruction to prefetch a complex data stream specified by the... |
| US-7,194,581 |
Memory channel with hot add/remove A memory agent may include a first port and a second port, wherein the memory agent is capable of detecting the presence of another memory agent on the second... |
| US-7,194,580 |
Disk array device, method of extending storage capacity and computer
program If a disk array device according to the invention initially has four disk devices, which is the smallest number of disk devices for RAID5 (3D+P), the storage... |
| US-7,194,579 |
Sparse multi-component files A file is striped across multiple filers, file servers or other devices, to create a sparsely striped multi-component file. Each filer stores one sparse... |
| US-7,194,578 |
Onboard indicator A system and method for indicating the service status of serviceable elements of a subassembly stores the service status in a memory using a host controller.... |
| US-7,194,577 |
Memory latency and bandwidth optimizations A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that... |
| US-7,194,576 |
Fetch operations in a disk drive control system A method and system for improving fetch operations between a micro-controller and a remote memory via a buffer manager in a disk drive control system comprising... |
| US-7,194,575 |
Automatic disk mirroring according to workload A disk volume access controlling method includes the steps of setting a threshold number of times of accesses from a computer to a predetermined disk volume per... |
| US-7,194,574 |
Searching small entities in a wide CAM A plurality of entities are stored in a single addressable location in a Content Addressable Memory (CAM). A column in a CAM entry is selected for storing an... |
| US-7,194,573 |
CAM-based search engine devices having advanced search and learn
instruction handling CAM-based search engine devices operate to reduce the occurrence of duplicate learned entries within a CAM database when processing search and learn (SNL)... |
| US-7,194,572 |
Memory system and method to reduce reflection and signal degradation Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced... |
| US-7,194,571 |
Microcomputer, programming method and erasing method The present invention provides a microcomputer wherein in a system which needs to respond to events developed at intervals each shorter than an erase/program... |
| US-7,194,570 |
Method and device for selecting the operating mode of an integrated
circuit A device for selecting an operating mode of an integrated circuit, comprising a ROM storing at least one predetermined value formed of data words, a non-volatile... |
| US-7,194,569 |
Method of re-formatting data A data structure is disclosed. The data structure includes a data descriptor record. In turn, the data descriptor record includes a type field, a base address... |
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