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| Patent # | Description |
|---|---|
| US-7,203,919 |
Retiming circuits using a cut-based approach Methods and apparatus for retiming an integrated circuit are described. According to certain embodiments, the retiming comprises performing a timing analysis for... |
| US-7,203,918 |
Delay and signal integrity check and characterization A method for performing a signal integrity and delay check for circuit simulations is disclosed. Nodes of the circuit are selected and an optimization parameter... |
| US-7,203,917 |
Efficient distributed SAT and SAT-based distributed bounded model checking There is provided a method of solving a SAT problem comprising partitioning SAT-formula clauses in the SAT problem into a plurality of partitions. Each of said... |
| US-7,203,916 |
System, method and program product for positioning I/O pads on a chip Under the present invention, a proposed placement of I/O pads into one or more groups on a chip analyzed. Specifically, using resources such as a control file,... |
| US-7,203,915 |
Method for retiming in the presence of verification constraints A method, system and computer program product for performing retiming in the presence of constraints are disclosed. The method comprises receiving an initial... |
| US-7,203,914 |
Timing circuit cad A method of generating a design for timing circuitry having plural rotary travelling wave component circuit sections, comprises the steps of first dividing an... |
| US-7,203,913 |
Semiconductor integrated circuit device, method of testing the same,
database for design of the same and method... Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to... |
| US-7,203,912 |
Compiling memory dereferencing instructions from software to hardware in
an electronic design Electronic system functionality can be initially implemented as software code (e.g., in programming languages such as C, C++ or Pascal) and selectively converted... |
| US-7,203,911 |
Altering a display on a viewing device based upon a user proximity to the
viewing device A method, apparatus, and article of manufacture altering a displayed image presented to a user on a viewing device using the proximity of the user to the viewing... |
| US-7,203,910 |
Method and apparatus for organizing and processing information using a
digital computer A method and apparatus for organizing and processing pieces of interrelated information (or "thoughts") using a digital computer is disclosed. The invention... |
| US-7,203,909 |
System and methods for constructing personalized context-sensitive portal
pages or views by analyzing patterns... The present invention relates to a system and methodology to assist users with data access activities and that includes such activities as routine web browsing... |
| US-7,203,908 |
Character communication device A character communication device which is connected to a network and enables at least communication by using characters. The device comprises a candidate term... |
| US-7,203,907 |
Multi-modal synchronization A first-modality gateway and a second-modality gateway are synchronized, with both gateways interfacing between a user and a server system. The synchronizing... |
| US-7,203,906 |
Supplying notifications related to supply and consumption of user context
data Techniques are described for providing information about a current state that is modeled with multiple state attributes. In some situations, the providing... |
| US-7,203,905 |
System and method for platform independent desktop lockdown A system and method that provides a platform-neutral shell application for a user interface is provided. The platform neutral shell application is performed in a... |
| US-7,203,904 |
Data processing system using a dual monitor and controlling method of
network system thereby Disclosed is a data processing system using a dual monitor, on which separate contents are displayed respectively, as a display device. The data processing... |
| US-7,203,903 |
System and methods for spacing, storing and recognizing electronic
representations of handwriting, printing and... A system for spacing, storing and recognizing electronic representations of handwriting and printing comprises a central processing unit that couples with a... |
| US-7,203,902 |
Method and apparatus for document composition A method of composing a document is disclosed which comprises defining a plurality of content portions to be fitted to the document, defining a content layout... |
| US-7,203,901 |
Small form factor web browsing A large web page is analyzed and partitioned into smaller sub-pages so that a user can navigate the web page on a small form factor device. The user can browse... |
| US-7,203,900 |
Apparatus and method for inserting blank document pages in a print layout
application This invention relates to a document processing apparatus which edits document data which can define a desired section using an original page as a unit of... |
| US-7,203,899 |
Systems and methods for assessing user success rates of accessing
information in a collection of contents Systems and methods measure the navigability of a web site by determining the rate at which simulated users absorb information scent. This note can be viewed as... |
| US-7,203,898 |
Document processing method and apparatus A document processing technique using a computer having an application program for creating application data and a layout program for performing layout... |
| US-7,203,897 |
Method and apparatus for encoding and decoding data A base model matrix is defined for the largest code length of each code rate. The set of shifts {p(i,j)} in the base model matrix are used to determine the shift... |
| US-7,203,896 |
High-efficiency error detection and/or correction code A method for determining r error detection bits that can be associated with a word of m bits to be coded, including the step of calculating the product of a... |
| US-7,203,895 |
Error correction decoding method and apparatus An error correction decoding method and apparatus are provided. The error correction decoding method involves (a) outputting data corresponding to input... |
| US-7,203,894 |
Method of estimating reliability of decoded message bits A method of estimating the reliability of decoded message bits in a digital communications system is proposed. Message and tail bits are coded and transmitted... |
| US-7,203,893 |
Soft input decoding for linear codes A method of decoding soft input information related to a transmitted word of a linear block code (n, k) and providing hard or soft output information is... |
| US-7,203,892 |
Row-diagonal parity technique for enabling efficient recovery from double
failures in a storage array A "row-diagonal" (R-D) parity technique reduces overhead of computing diagonal parity for a storage array adapted to enable efficient recovery from the... |
| US-7,203,891 |
Information storage medium on which drive data is recorded, and method of
recording information on the... An information storage medium includes a drive zone having a plurality of physical clusters or ECC blocks. When new drive data is recorded in the drive zone, the... |
| US-7,203,890 |
Address error detection by merging a polynomial-based CRC code of address
bits with two nibbles of data or data... A memory system provides data error detection and correction and address error detection. A Single-byte Error-Correcting/Double-byte Error-Detecting (SbEC/DbED)... |
| US-7,203,889 |
Error correction for memory A memory controller includes a write data module to write user data, parity information, and error correction information in a memory. The memory controller... |
| US-7,203,888 |
System and method for correcting linear block code The present invention is a correcting system for correcting a linear block code generated by coding an original data via a data coding process when a... |
| US-7,203,887 |
Method and system for routing in low density parity check (LDPC) decoders An approach is provided for decoding a low density parity check (LDPC) coded signal. Edge values associated with a structured parity check matrix used to... |
| US-7,203,886 |
Detecting and correcting corrupted memory cells in a memory A data storage comprises memory having a plurality of memory cells operative to retain data until read. A buffer cooperates, under the control of an address and... |
| US-7,203,885 |
Safety protocol for industrial controller Messages in a high reliability industrial control system are associated with safety messages that enable reliable detection of data errors caused during... |
| US-7,203,884 |
Shaped spectral coding and recording systems therefor In the MSN encoded form, the symbols of each block of the present invention define a running digital sum (RDS) value, defined as RDS([a.sub.0a.sub.1 . . .... |
| US-7,203,883 |
Integrated circuit An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input... |
| US-7,203,882 |
Clustering-based approach for coverage-directed test generation A coverage-directed test generation technique for functional design verification relies on events that are clustered according to similarities in the way that... |
| US-7,203,881 |
System and method for simulating system operation One embodiment of the invention provides a method for simulating the operation of a system. The method includes providing a fault tree representation of the... |
| US-7,203,880 |
Generating an abbreviated netlist including pseudopin inputs and output
nodes A method generates test vectors for a customer designed integrated circuit having an embedded vendor circuit. The embedded vendor circuit has a proprietary... |
| US-7,203,879 |
Built-in-test diagnostic and maintenance support system and process A diagnostic and maintenance support system and process are provided for performing tests, collecting Built-In-Test (BIT) log data from systems, analyzing fault... |
| US-7,203,878 |
System and method for performing predictable signature analysis in the
presence of multiple data streams A computer system may include several integrated circuits and a routing circuit configured to route several data streams between the integrated circuits. The... |
| US-7,203,877 |
Failure analysis and testing of semi-conductor devices using intelligent
software on automated test equipment (ATE) The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a... |
| US-7,203,876 |
Method and apparatus for controlling AC power during scan operations in
scannable latches A method and apparatus are provided for implementing AC power dissipation control during scan operations in scannable latch designs. A scannable latch has a... |
| US-7,203,875 |
Test systems and methods with compensation techniques The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the... |
| US-7,203,874 |
Error detection, documentation, and correction in a flash memory device A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating... |
| US-7,203,873 |
Asynchronous control of memory self test A memory logic built-in self-test ("BIST") includes slow speed controller-to-collar signals, while allowing collars to test memories at full speed. A controller... |
| US-7,203,872 |
Cache based physical layer self test A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to... |
| US-7,203,871 |
Arrangement in a network node for secure storage and retrieval of encoded
data distributed among multiple... Data is stored using multiple selected network nodes in a network based on encoding of the data into multiple distinct encoded data units according to a... |
| US-7,203,870 |
Semiconductor memory unit with repair circuit A semiconductor memory unit with a repair circuit includes a controller, a 2-to-1 selector, an address decoder and an address comparator. The controller supplies... |
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