| Patent # | Description |
|---|---|
| US-7,203,869 |
Test stream generating method and apparatus for supporting various
standards and testing levels A method and apparatus for generating a test stream wherein tests of digital TV software at various levels and various digital broadcast standards can be... |
| US-7,203,868 |
Dynamic monitoring of resources using snapshots of system states One embodiment of the invention is a method for dynamically monitoring resources. A request of a user to monitor at least one specified resource is sent to a... |
| US-7,203,867 |
Processor system, processor and arithmetic processing method A processor system, comprising: a first program storage which stores a first program; a second program storage which stores a second program; a program counter... |
| US-7,203,866 |
Method and apparatus for a programming language having fully undoable,
timed reactive instructions A method and apparatus for providing an undoable programming language. More specifically the present invention relates to providing a fully undoable programming... |
| US-7,203,865 |
Application level and BIOS level disaster recovery The present invention is directed to a BIOS level and application level recovery of an information handling system. A method for recovering from a failure of an... |
| US-7,203,864 |
Method and system for clustering computers into peer groups and comparing
individual computers to their peers A method and system for identifying clusters of similarly-configured computers. The method, for example, comprises gathering system and business configuration... |
| US-7,203,863 |
Distributed transaction state management through application server
clustering A method, system, and computer program product stores transaction state information in application server process cluster information, eliminating transaction... |
| US-7,203,862 |
Methods for controlling storage devices controlling apparatuses A storage device controller including: channel control portions each including a circuit board on which a file access processing portion for receiving... |
| US-7,203,861 |
Method and system for remotely backing up a computer memory utilizing a
global communications network Embodiments of the present invention relate to a method and system for remotely backing-up computer memories utilizing a global communications network. An... |
| US-7,203,860 |
Clock recovery circuit for high-speed data signal transmission A clock recovery circuit has a phase comparator circuit, a phase adjusting circuit, and a duty cycle correction circuit. The phase comparator circuit carries out... |
| US-7,203,859 |
Variable clock configuration for switched op-amp circuits A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted... |
| US-7,203,858 |
Program clock synchronization in multimedia networks A method may include sampling a receive frequency at which information received over a communication link is played. The method may also include sampling a... |
| US-7,203,857 |
On-demand clock switching First and second functional circuit blocks (FCBs) control the operation of a clock circuits coupled thereto in dependence upon processing requirements of the... |
| US-7,203,856 |
Mobile computer with desktop type processor A mobile computer with a desktop type processor. The mobile computer further includes a battery, a current sensor, and a clock generator. The battery supplies a... |
| US-7,203,855 |
Power-saving control circuitry of electronic device and operating method
thereof A power-saving control circuitry of an electronic device is provided. The power-saving control circuitry comprises a power control circuit, an oscillator, a... |
| US-7,203,854 |
System for reconfiguring a computer between a high power and high
functionality configuration and a low power... An intermittent computing system state and intermittent computing module is described for a power-constrained personal computer. In the intermittent computing... |
| US-7,203,853 |
Apparatus and method for low latency power management on a serial data
link An apparatus and method for low latency power management on a serial data link are described. In one embodiment, the method includes the detection of an... |
| US-7,203,852 |
System and process for making power readily available to newly added
computers A system for and a process of controlling power supplied to a group of computers. The power available is determined, and the total power requirement of the group... |
| US-7,203,851 |
Method and apparatus for detecting and supplying power by a first network
device to a second network device A first network device supplies power to a second network device in communication therewith. The first network device comprises a physical layer device which... |
| US-7,203,850 |
Power management for a network utilizing a vertex/edge graph technique A power management technique for a network including a plurality of computing devices. The power management technique includes identifying an order in which one... |
| US-7,203,849 |
Method and system for distributing power to networked devices One embodiment disclosed relates to a system for power distribution to network devices. The system includes a plurality of network switches each having an... |
| US-7,203,848 |
Electrical apparatus, program for controlling electrical apparatus, and
method for controlling electrical apparatus A printer changes a setup menu in such a way as to enable a user to select an automatic mode for automatically setting a switching time for switching to a power... |
| US-7,203,847 |
Power supply for central processing unit A power supply and method for a central processing unit (CPU). The power can include a first power supply circuit such as a DC/DC converter for supplying a... |
| US-7,203,846 |
System and method for intelligent control of power consumption of
distributed services during periods of... A system and method intelligently control power consumption of distributed services using a computer system that provides independent computing elements each... |
| US-7,203,845 |
Multiple trust modes for handling data A user is presented with multiple modes of operation, such that the multiple modes of operation define different trust options for handling data (such as login... |
| US-7,203,844 |
Method and system for a recursive security protocol for digital copyright
control Systems and methods are described which utilize a recursive security protocol for the protection of digital data. These may include encrypting a bit stream with... |
| US-7,203,843 |
Method and system for transferring data A system is provided for improving security during data transfer. A transmitter side transfer controller (12) divides data to be transferred into a plurality of... |
| US-7,203,842 |
Method and apparatus for secure configuration of a field programmable gate
array A field programmable gate array (70) has security configuration features to prevent monitoring of the configuration data for the field programmable gate array.... |
| US-7,203,841 |
Encryption in a secure computerized gaming system The present invention provides an architecture and method for a gaming-specific platform that features secure storage (354) and verification (366) of game code... |
| US-7,203,840 |
Access control for interactive learning system A technique to control access to computer network resources at a computer facility permits a user to interact with the computer facility through a computer node... |
| US-7,203,839 |
Method for providing secure access to information held in a shared
repository A method for providing secure access to information held in a shared repository, for example to electronic business cards stored on a server. A data owner... |
| US-7,203,838 |
System and method for authenticating a web page The present invention provides for an icon with an additional level of functionality that allows a user to validate that current information (e.g., a web page)... |
| US-7,203,837 |
Methods and systems for unilateral authentication of messages A system and method for authentication verifies the address of an information sender based on the sender's address, public key, and a digital signature. A... |
| US-7,203,836 |
Method and device for the mutual authentication of components in a network
using the challenge-response method A method for mutual authentication of components in a network using a challenge-response method, including the steps of requesting at least one data pair... |
| US-7,203,835 |
Architecture for manufacturing authenticatable gaming systems An architecture is described to manufacture console-based gaming systems in a manner that allows them to be authenticated to a remote entity for online... |
| US-7,203,834 |
Method of updating encryption keys in a data communication system The invention discloses a method of updating, in nodes on both ends of a secure link, the encryption key they share to encrypt and decrypt data. When having to... |
| US-7,203,833 |
History based rights computation for managed code In the access control model of security, an access control matrix associates rights for operations on objects with subjects. An approach for assigning rights to... |
| US-7,203,832 |
Network system This network system includes a first device serving as a shared resource connected to a network, a second device connected to the network and including an object... |
| US-7,203,831 |
System and method for performing remote BIOS updates A system and method for remotely updating a system BIOS. The method includes the steps of providing an updated BIOS to the remote computer system, storing the... |
| US-7,203,830 |
Apparatus and method to decrease boot time and hibernate awaken time of a
computer system A method and apparatus to decrease the boot time and the hibernate awaken time of a computer system is presented. Static and dynamic configuration data is stored... |
| US-7,203,829 |
Apparatus and method for initializing coprocessor for use in system
comprised of main processor and coprocessor An apparatus and method for initializing a coprocessor for use in system comprised of a main processor and coprocessor. The apparatus can be provided with fewer... |
| US-7,203,828 |
Use of NAND flash for hidden memory blocks to store an operating system
program A memory device has a plurality of memory blocks utilized to store data. One of the blocks is used as a hidden memory block to store an operating system program,... |
| US-7,203,827 |
Link and fall-through address formation using a program counter portion
selected by a specific branch address bit A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at... |
| US-7,203,826 |
Method and apparatus for managing a return stack A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller... |
| US-7,203,825 |
Sharing information to reduce redundancy in hybrid branch prediction A hybrid branch predictor is disclosed. The predictor includes prediction aiding information, a plurality of branch predictors to provide a plurality of branch... |
| US-7,203,824 |
Apparatus and method for handling BTAC branches that wrap across
instruction cache lines A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch... |
| US-7,203,823 |
Partial and start-over threads in embedded real-time kernel Methods and apparatus for implementing partial and start-over threads in a kernel of an operating system are disclosed. In a computing system having at least one... |
| US-7,203,822 |
Unprivileged context management Embodiments of the present invention provide full benefit of the cover instruction provided by the Intel IA-64 architecture to code running at less than highest... |
| US-7,203,821 |
Method and apparatus to handle window management instructions without post
serialization in an out of order... A method and apparatus for handling window management instructions without post serialization in an out-of-order multi-issue processor includes an instruction... |
| US-7,203,820 |
Extending a register file utilizing stack and queue techniques In a set of registers, each individually addressable by register operations using a corresponding register identification, at least one register of the set of... |