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| Patent # | Description |
|---|---|
| US-7,212,466 |
Producing amplitude values for controlling pixel illumination on a sonar
display A method and apparatus for producing an amplitude value for use in controlling illumination of a pixel on a display, in response to a sampled sonar signal... |
| US-7,212,465 |
Clock signal generation apparatus for use in semiconductor memory device
and its method A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a... |
| US-7,212,464 |
Semiconductor memory device having a plurality of latch circuits coupled
to each read amplifier A semiconductor memory device includes: a plurality of memory cells arranged in a matrix; a memory cell array divided into a plurality of blocks; a plurality of... |
| US-7,212,463 |
Method and system of operating mode detection A system and method of providing a voltage to a non-volatile memory. The system includes an output pin to provide an output voltage to a non-volatile memory and... |
| US-7,212,462 |
Structure and method for suppressing sub-threshold leakage in integrated
circuits Techniques for reducing leakage power in the transistors of integrated circuits are provided. Suppressing sub-threshold leakage techniques can be applied to... |
| US-7,212,461 |
Semiconductor memory device A memory device conducts a stable data access operation by removing glitch component in an internal clock outputted after a completion of self-refresh. This... |
| US-7,212,460 |
Line amplifier to supplement line driver in an integrated circuit A method and circuitry for boosting a driven signal along a circuit line so as to reduce RC delays is disclosed. In one embodiment, the circuitry includes a line... |
| US-7,212,459 |
Unified multilevel cell memory A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common... |
| US-7,212,458 |
Memory, processing system and methods for use therewith A memory includes a selected bitline coupled to the array of memory cells. A column multiplexer passes a signal on the selected bitline to a sense amplifier... |
| US-7,212,457 |
Method and apparatus for implementing high speed memory Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is... |
| US-7,212,456 |
Apparatus for dynamically repairing a semiconductor memory An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing... |
| US-7,212,455 |
Decoder of semiconductor memory device A column decoder in a semiconductor memory device in which address setting cannot be performed but only a serial access can be performed. The column decoder is... |
| US-7,212,454 |
Method and apparatus for programming a memory array A method and apparatus for programming a memory array are disclosed. In one embodiment, after each word line is programmed, an attempt is made to detect a defect... |
| US-7,212,453 |
Semiconductor memory having an error correction function Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell... |
| US-7,212,451 |
Column selection signal generator of semiconductor memory device A column selection signal generator of a semiconductor memory device is configured to maintain a predetermined pulse width of a column selection signal... |
| US-7,212,450 |
FeRAM having differential data Disclosed is a non-volatile ferroelectric memory device having differential data, the device including: a plurality of cell array block groups having a hierarchy... |
| US-7,212,449 |
Data output device of semiconductor memory device There is provided a data output device for stably operating in a high frequency circumstance. The data output device includes a selection unit for receiving a... |
| US-7,212,448 |
Method and apparatus for multiple context and high reliability operation
of programmable logic devices A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of... |
| US-7,212,447 |
NAND flash memory cell programming A flash memory device, such as a NAND flash, having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A... |
| US-7,212,446 |
Counteracting overtunneling in nonvolatile memory cells using charge
extraction control Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a... |
| US-7,212,445 |
Non-volatile memory and method with improved sensing A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells... |
| US-7,212,444 |
Semiconductor nonvolatile memory device An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor... |
| US-7,212,443 |
Non-volatile memory and write method of the same A non-volatile memory in which a plurality of memory cells connected to a same word line are entirely written with data. Source lines SL separated from each... |
| US-7,212,442 |
Structure for directly burning program into motherboard The present invention relates to a structure for directly burning a program into a motherboard comprising a burning plate having a series connected first... |
| US-7,212,441 |
Non volatile semiconductor memory device In a nonvolatile semiconductor memory device, the increase of the capacity of a nonvolatile semiconductor memory inevitably causes the power supply circuits... |
| US-7,212,440 |
On-chip data grouping and alignment The invention describes the method for regrouping data read from multi-sector pages inside a memory chip. As a result, garbage collection operation time greatly... |
| US-7,212,439 |
NAND flash memory device and method of programming the same Provided is directed to a NAND flash memory device and a method of programming the same, which can improve integration of the device by removing a common source... |
| US-7,212,438 |
Semiconductor device and method of operating a semiconductor device The invention considers a non-volatile semiconductor memory device comprising a first and second floating gate transistor, which are coupled in series. Each... |
| US-7,212,437 |
Charge coupled EEPROM device and corresponding method of operation This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor... |
| US-7,212,436 |
Multiple level programming in a non-volatile memory device The programming method of the present invention minimizes program disturb in a non-volatile memory device by initially programming a lower page of a memory... |
| US-7,212,435 |
Minimizing adjacent wordline disturb in a memory device A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected... |
| US-7,212,434 |
Semiconductor memory device with MOS transistors, each including a
floating gate and a control gate, and a... A semiconductor memory device includes memory cells, a memory cell array, word lines, latch circuits, first row decoders, second row decoders, first isolating... |
| US-7,212,433 |
Ferromagnetic layer compositions and structures for spin polarized memory
devices, including memory devices Ferromagnetic materials for use with spin memory and logic devices include a geometry and composition adapted to increase spin injection efficiency and/or reduce... |
| US-7,212,432 |
Resistive memory cell random access memory device and method of
fabrication A resistive memory cell random access memory device and method for fabrication. In one embodiment, the invention relates to a resistive memory cell random access... |
| US-7,212,431 |
Nonvolatile ferroelectric memory device and control method thereof A nonvolatile ferroelectric memory device and a control method thereof are provided to control read/write operations of memory cell arrays whose channel... |
| US-7,212,430 |
Semiconductor memory A ferroelectric memory has a plurality of memory cells respectively having a cell transistor and ferroelectric capacitor whose one terminal is connected with the... |
| US-7,212,429 |
Nonvolatile ferroelectric memory device A nonvolatile ferroelectric memory device comprises a cell array block, a sense amplifier unit, a main amplifier unit and a data bus unit. The ferroelectric... |
| US-7,212,428 |
FeRAM having differential data A non-volatile ferroelectric memory device having differential datacomprises a plurality of cell array blocks and a data buffer unit. Each of the plurality of... |
| US-7,212,427 |
Ferroelectric memory A ferroelectric memory including a bit line pair, a drive line parallel to and located between the bit lines, and an associated memory cell. The memory cell... |
| US-7,212,426 |
Flash memory system capable of inputting/outputting sector data at random A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a... |
| US-7,212,425 |
Semiconductor integrated circuit device A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps... |
| US-7,212,424 |
Double-high DIMM with dual registers and related methods One memory module includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first... |
| US-7,212,423 |
Memory agent core clock aligned to lane Memory apparatus and methods align a core clock for a memory agent to one of a plurality of lanes. A memory agent may have logic circuit between the lanes and a... |
| US-7,212,422 |
Stacked layered type semiconductor memory device To provide laminated type semiconductor memory devices that can improve the yield of chips without complicating wirings and components. There are provided a... |
| US-7,212,421 |
Combination feedback controller and power regulator using same A combination controller incorporates features of a classic controller and a state space controller to function as a hybrid controller unit. The PID portion of... |
| US-7,212,420 |
Universal serial bus voltage transformer The present invention provides a universal serial bus (USB) voltage transformer, which comprises a main body, a transformer circuit unit, and several connectors.... |
| US-7,212,419 |
Adaptively configured and autoranging voltage transformation module arrays A method and apparatus for adaptively configuring an array of voltage transformation modules is disclosed. The aggregate voltage transformation ratio of the... |
| US-7,212,418 |
Synchronous rectifier control circuit A synchronous rectifier control circuit improves energy conversion efficiency and uses a signal produced by a secondary winding of a transformer in a rectifier... |
| US-7,212,417 |
Dual-mode switching DC-to-DC converter A transformer has a primary winding connected to a pair of DC input terminals via an active switch, and a secondary winding connected to a pair of DC output... |
| US-7,212,416 |
Switching power supply device and switching method A current flowing through a reactor flows through a resistor, which generates a voltage in accordance with the value of the current. As the voltage generated by... |
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