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| Patent # | Description |
|---|---|
| US-7,213,169 |
Method and apparatus for performing imprecise bus tracing in a data
processing system having a distributed memory An apparatus for performing imprecise bus tracing in a distributed memory symmetric multiprocessor system is disclosed. The apparatus includes a bus trace macro... |
| US-7,213,168 |
Safety controller providing for execution of standard and safety control
programs A safety controller may execute both standard and safety programs using shared architecture in which two processors symmetrically execute the safety program and... |
| US-7,213,167 |
Redundant state machines in network elements A mechanism for providing one or more passive state machines behaving in the same manner as an active state machine so that one of the passive machines will take... |
| US-7,213,166 |
In-place data transformation for fault-tolerant disk storage systems A fault tolerant method transforms physically contiguous data in-place on a disk by partitioning the physically contiguous data into an empty region physically... |
| US-7,213,165 |
Host I/O performance and availability of a storage array during rebuild by
prioritizing I/O requests Improved host I/O performance and availability of a storage array during rebuild is obtained by prioritizing I/O requests. In one embodiment, rebuild I/O... |
| US-7,213,164 |
Contents furnishing system Even if contents data distributed over a network are once destroyed, the contents data are restored, as the copyright protection is maintained. A PC memorizes... |
| US-7,213,163 |
Restoring power in a hot swappable multi-server data processing
environment A data processing network includes a set of servers, at least one switch module to interconnect the servers, and a management module. The management module... |
| US-7,213,162 |
Data processing apparatus A data processing apparatus has a first processing unit for processing an input data, a second processing unit responsive to the data processed by the first... |
| US-7,213,161 |
System for controlling the clock to each of a plurality of protocol
circuits of an interface control integrated... In an interface control semiconductor integrated circuit including a plurality of protocol circuits for processing a protocol such as AV- or PC-oriented... |
| US-7,213,160 |
Power management apparatus, power management method, and power management
system When causing a power saving mode to return by inputting a return signal, power is supplied to a device to which suppliance of power has been cut off. In this... |
| US-7,213,159 |
Method for testing and verifying power management features of computer
system A method of automatically testing and verifying power management features of a computer system in different modes including Standby, Hibernate, Shutdown, and... |
| US-7,213,158 |
Distributed autonomic backup The disclosed methods provide a reliable and secure method of automatically backing up a client's data on a personal computer by using excess storage capacity on... |
| US-7,213,157 |
Integrated circuit for digital rights management An ASIC for implementing digital rights management includes a processor for requesting encrypted digital data from a server and decrypting the data, and a player... |
| US-7,213,156 |
Contents data transmission/reception system, contents data transmitter,
contents data receiver and contents... An object of the invention is to prevent original high quality contents data from being illegally obtained by extracting encryption breaking information from... |
| US-7,213,155 |
Recording medium, recording and/or reproducing method for record medium,
and recording and/or reproducing... A recording and reproducing method for a record medium including the steps of reading type information from the record medium when data is recorded to or... |
| US-7,213,154 |
Query data packet processing and network scanning method and apparatus A method for detecting within a networked computer a target vulnerability such as a Trojan Horse residing therein is disclosed, wherein the vulnerability is... |
| US-7,213,153 |
Application program interface interception system and method A method of intercepting application program interface, including dynamic installation of associated software, within the user portion of an operating system. An... |
| US-7,213,152 |
Modular bios update mechanism A modular BIOS update mechanism provides a standardized method to update options ROMs and to provide video and processor microcode upgrades in a computer system... |
| US-7,213,151 |
Method and computer system for encoding of information into a
representation The present invention relates to a computer system and to a method for encoding of information into a representation comprising a plurality of segments, the... |
| US-7,213,150 |
Method and apparatus for secure message queuing One embodiment of the present invention provides a system that facilitates secure messaging. The system starts by creating a message at an origin. Next, the... |
| US-7,213,149 |
Message authentication For the authentication of messages communicated in a distributed system from an originator to a destination a keyed-hashing technique is used according to which... |
| US-7,213,148 |
Apparatus and method for a hash processing system using integrated message
digest and secure hash architectures A hash processing system and method for reducing the number of clock cycles required to implement the SHA1 and MD5 hash algorithms by using a common hash memory... |
| US-7,213,147 |
Methods and apparatus for managing secure collaborative transactions Different levels of security are provided in a security system so that users can decide the security level of their own communications. Users can choose a low... |
| US-7,213,146 |
System and method for establishing security profiles of computers A computer system enables a user to define the system's security profile while automatically detecting whether the security profile being defined creates data... |
| US-7,213,145 |
Method and apparatus for secure internet protocol communication in a call
processing system Techniques for providing secure communications between two or more end units of a call processing system via a call complex or other communication system switch.... |
| US-7,213,144 |
Efficient security association establishment negotiation technique A Security Association establishment negotiation technique includes forwarding identifying information from a Mobile Node via a first interface to a first... |
| US-7,213,143 |
Security over a network According to one aspect of the present invention there is provided a method of preparing second protocol data for transmitting over a first protocol network... |
| US-7,213,142 |
System and method to initialize registers with an EEPROM stored boot
sequence A system and method to initialize registers with an EEPROM stored boot sequence is described. The method includes reading configuration records from an EEPROM... |
| US-7,213,141 |
Storage subsystem and storage controller A storage subsystem and a storage controller adapted to take advantage of high data transfer rates of fibre channels while offering enhanced reliability and... |
| US-7,213,140 |
Method for self-starting a computer According to the claimed invention, a computer is disclosed. The computer comprises a first memory for storing a BIOS, a clock for tracking time, a second memory... |
| US-7,213,139 |
System for gathering and storing internal and peripheral components
configuration and initialization... A method of computer start-up, using the configuration information of the internal and peripheral components of the computer system and information required for... |
| US-7,213,138 |
Data transmission apparatus, system and method, and image processing
apparatus A data transmission system where an image providing device and a printer are directly connected by a 1394 serial bus, a command is sent from the image providing... |
| US-7,213,137 |
Allocation of processor bandwidth between main program and interrupt
service instruction based on interrupt... The method and apparatus feature detecting an interrupt service request; storing into an instruction cache interrupt service instructions in response to... |
| US-7,213,136 |
Apparatus and method for redundant zero micro-operation removal A method and apparatus for redundant zero micro-operation removal. In one embodiment, the method includes the identification of a predetermined ... |
| US-7,213,135 |
Method using a dispatch flush in a simultaneous multithread processor to
resolve exception conditions The processing of instructions from multiple threads using a shared dispatch pipeline is controlled by invoking a dispatch flush operation wherein instructions... |
| US-7,213,134 |
Using thread urgency in determining switch events in a temporal
multithreaded processor unit A processing unit of the invention has multiple instruction pipelines for processing multi-threaded instructions. Each thread may have an urgency associated with... |
| US-7,213,133 |
Method and apparatus for avoiding write-after-write hazards in an
execute-ahead processor One embodiment of the present invention provides a system that avoids write-after-write (WAW) hazards while speculatively executing instructions. The system... |
| US-7,213,132 |
System and method for providing predicate data to multiple pipeline stages A processing system provides predicate data that indicates whether instructions processed by a processor pipeline should be executed by the pipeline. In... |
| US-7,213,131 |
Programmable processor and method for partitioned group element selection
operation A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single... |
| US-7,213,130 |
Instruction rollback processor system, an instruction rollback method and
an instruction rollback program An instruction rollback processor system according to the present invention is provided. The instruction rollback processor system includes: an instruction... |
| US-7,213,129 |
Method and system for a two stage pipelined instruction decode and
alignment using previous instruction length A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream.... |
| US-7,213,128 |
Storing and transferring SIMD saturation history flags and data size A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information pursuant to instruction execution. A... |
| US-7,213,127 |
System for producing addresses for a digital signal processor A system for generating addresses for a digital signal processor in which the program instructions include a code for accessing a memory associated with said... |
| US-7,213,126 |
Method and processor including logic for storing traces within a trace
cache A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including... |
| US-7,213,125 |
Method for patching virtually aliased pages by a virtual-machine monitor Various embodiments of the present invention are directed to methods by which a virtual-machine monitor can introduce branch instructions, in order to emulate... |
| US-7,213,124 |
Method for allocating storage area to virtual volume A system for storing data includes a virtualization apparatus coupled to a computer and to a plurality of storage devices. In response to a request from the... |
| US-7,213,123 |
Method and apparatus for mapping debugging information when debugging
integrated executables in a heterogeneous... The present invention provides for the employment of a dynamic debugger for a parallel processing environment. This is achieved by dynamically updating mapping... |
| US-7,213,122 |
Controlling the generation and selection of addresses to be used in a
verification environment The generation and selection of addresses to be employed in a verification environment are tightly coupled to ensure that the addresses a user desires to be... |
| US-7,213,121 |
Memory device having asynchronous/synchronous operating modes An integrated circuit memory device comprises a memory array to store data, a circuit to output the data at a pin, and a register to store a value that indicates... |
| US-7,213,120 |
Circuit for prevention of unintentional writing to a memory, and
semiconductor device equipped with said circuit A circuit for prevention of unintentional writing to a memory prevents unintentional writing to a nonvolatile memory, after a recovery from a transitory power... |
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