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| Patent # | Description |
|---|---|
| US-7,372,764 |
Logic device with reduced leakage current A logic device operates with reduced leakage current. Controllability is achieved by using a reference voltage to control the amount of leakage reduction. A... |
| US-7,372,763 |
Memory with spatially encoded data storage In some embodiments, the invention provides a chip with at least one memory circuit that comprises a majority voter circuit with first and second digitally... |
| US-7,372,762 |
Semiconductor memory device The present invention is related to a semiconductor memory device improving refresh performance by reliably generating an internal voltage. The internal voltage... |
| US-7,372,761 |
Semiconductor device, nonvolatile semiconductor memory, system including a
plurality of semiconductor devices... The object is to avoid an erroneous operation during a term in which an initialization is performed when a command is input.After a power source is turned on, a... |
| US-7,372,760 |
Semiconductor device and entry into test mode without use of unnecessary
terminal A semiconductor device includes a first power supply terminal, a second power supply terminal, a comparison circuit coupled to the first power supply terminal... |
| US-7,372,759 |
Power supply control circuit and controlling method thereof The present invention provides a power supply control circuit and a control method thereof, capable of securing an accurate operation of a GIO in a burst data... |
| US-7,372,758 |
Semiconductor memory device, method for controlling the same, and mobile
electronic device A memory cell array employs a memory element as a memory cell. The memory element is constructed of a gate electrode formed via a gate insulation film on a... |
| US-7,372,757 |
Magnetic memory device with moving magnetic domain walls A magnetic memory device includes a plurality of first metal lines arranged in parallel on a substrate and including a plurality of magnetic domains with... |
| US-7,372,756 |
Non-skipping auto-refresh in a DRAM In a dynamic random access memory device, an auto-refresh method comprises receiving a command for the memory device to operate in a half-density mode. This... |
| US-7,372,755 |
On-chip storage memory for storing variable data bits An improved on-chip storage memory and method for storing variable data bits, the memory including an on-chip storage memory system for storing variable data... |
| US-7,372,754 |
Method and apparatus for controlling slope of word line voltage in
nonvolatile memory device A nonvolatile memory device includes a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines, a... |
| US-7,372,753 |
Two-cycle sensing in a two-terminal memory array having leakage current A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected... |
| US-7,372,752 |
Test mode controller A test mode controller is capable of reducing a chip area and unnecessary current consumption by integrally constructing latch units of the two test circuits.... |
| US-7,372,751 |
Using redundant memory for extra features Apparatus and methods are provided. A memory device has a memory array comprising primary and redundant portions. A redundancy circuit is coupled to the memory... |
| US-7,372,750 |
Integrated memory circuit and method for repairing a single bit error The invention relates to an integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and having a... |
| US-7,372,749 |
Methods for repairing and for operating a memory component In a method for repairing a memory component, data retention times of regular memory cells are determined. Weak regular memory cells having a data retention time... |
| US-7,372,748 |
Voltage regulator in a non-volatile memory device System and method for controlling voltage in a non-volatile memory system is provided. The system includes a voltage regulator that monitors an output voltage... |
| US-7,372,747 |
Flash memory device and voltage generating circuit for the same A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a... |
| US-7,372,746 |
Low voltage sensing scheme having reduced active power down standby
current A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may... |
| US-7,372,745 |
Semiconductor memory device with no latch error A dynamic random access memory (DRAM) includes a data signal input circuit configured to input a data signal in response to a data control signal, and a data... |
| US-7,372,744 |
Memory system which copies successive pages, and data copy method therefor A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control... |
| US-7,372,743 |
Controlling a nonvolatile storage device A control method for a nonvolatile storage device having a storage mode in which in a memory cell provided with a trapping dielectric layer 1-bit data is stored... |
| US-7,372,742 |
Memory block erasing in a flash memory device The erase and verify method performs an erase operation and an erase verify read operation. If the erase verify read operation fails because unerased memory... |
| US-7,372,741 |
Nonvolatile memory apparatus having a processor and plural memories one or
more of which is a nonvolatile... A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality... |
| US-7,372,740 |
Semiconductor memory device Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit... |
| US-7,372,739 |
High voltage generation and regulation circuit in a memory device An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an... |
| US-7,372,738 |
Flash memory device with reduced erase time A NOR flash memory device comprises a memory cell array, a row selection circuit adapted to drive wordlines in the memory cell array with a wordline voltage... |
| US-7,372,737 |
Nonvolatile memory and method of driving the same The nonvolatile memory according to the present invention can precisely read information included in a memory transistor subject to a shift phenomenon because... |
| US-7,372,736 |
Monolithic, combo nonvolatile memory allowing byte, page and block write
with no disturb and divided-well in... A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The... |
| US-7,372,735 |
Non-volatile semiconductor memory device A non-volatile semiconductor memory device includes a non-volatile memory element group having a first storage area which stores booting data and a second... |
| US-7,372,734 |
Methods of operating electrically alterable non-volatile memory cell A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a... |
| US-7,372,733 |
Non-volatile semiconductor memory device having different erase pass
voltages for respective memory sectors and... A non-volatile semiconductor memory device comprises a plurality of memory sectors arranged in different memory banks having different bulk regions. The memory... |
| US-7,372,732 |
Pulse width converged method to control voltage threshold (Vt)
distribution of a memory cell A method of operating on a plurality of non-volatile multi-level memory cells is disclosed. The memory cells have at least a first, second, third and fourth... |
| US-7,372,731 |
Flash memories with adaptive reference voltages Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their... |
| US-7,372,730 |
Method of reading NAND memory to compensate for coupling between storage
elements A method for reading a non-volatile memory arranged in columns and rows which reduces adjacent cell coupling, sometimes referred to as the Yupin effect. The... |
| US-7,372,729 |
High speed low voltage driver A high speed high and low voltage driver provides an output voltage without taxing a pumped voltage. The pumped voltage is used only when the output node has... |
| US-7,372,728 |
Magnetic random access memory array having bit/word lines for shared write
select and read operations A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit... |
| US-7,372,727 |
Magnetic cell and magnetic memory A magnetic cell includes: a first ferromagnetic layer whose magnetization is substantially fixed in a first direction; a second ferromagnetic layer whose... |
| US-7,372,726 |
Semiconductor memory A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at... |
| US-7,372,725 |
Integrated circuit having resistive memory A memory device including a memory cell, a first circuit, and a second circuit. The memory cell includes phase-change material. The first circuit is configured... |
| US-7,372,724 |
Method for accessing data on magnetic memory A method for accessing data on a magnetic memory is provided, wherein the data is accessed in a toggle mode. A first current line and a second current line are... |
| US-7,372,723 |
State save-on-power-down using GMR non-volatile elements The semiconductor industry seeks to reduce the risk of traditional volatile storage devices with improved non-volatile storage devices. The increased demand for... |
| US-7,372,722 |
Methods of operating magnetic random access memory devices including
heat-generating structures Methods may be provided for operating a magnetic random access memory (MRAM device including a magnetic tunnel junction structure and a heat generating layer.... |
| US-7,372,721 |
Segmented column virtual ground scheme in a static random access memory
(SRAM) circuit A static random access memory (SRAM) cell array is provided that reduces leakage current. The SRAM cell array is configured in a plurality of columns. Each of... |
| US-7,372,720 |
Methods and apparatus for decreasing soft errors and cell leakage in
integrated circuit structures Methods and apparatus are provided for decreasing soft errors and cell leakage in integrated circuit structures. The structures of the invention preferably... |
| US-7,372,719 |
DRAM semiconductor memory device with increased reading accuracy A DRAM semiconductor memory device with increased reading accuracy and a method for increasing the reading accuracy of a DRAM memory cell are provided. First and... |
| US-7,372,718 |
Storage and semiconductor device A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of... |
| US-7,372,717 |
Methods for resistive memory element sensing using averaging A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage... |
| US-7,372,716 |
Memory having CBRAM memory cells and method A memory cell arrangement has a plurality of memory cells of the CBRAM type and a programming apparatus, the memory cells being arranged along bit lines and each... |
| US-7,372,715 |
Architecture and method for NAND flash memory A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are... |
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