Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,373,572 |
System pulse latch and shadow pulse latch coupled to output joining
circuit In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system... |
| US-7,373,571 |
Achieving desired synchronization at sequential elements while testing
integrated circuits using sequential... A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated... |
| US-7,373,570 |
LSI device having scan separators provided in number reduced from signal
lines of combinatorial circuits A scan separator in a large scale integration device is made more extensive to suppress an increase in the circuit scale of the entire device. In one embodiment,... |
| US-7,373,569 |
Pulsed flop with scan circuitry In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and... |
| US-7,373,568 |
Scan insertion An integrated circuit comprises n storage elements, arranged to form a scan chain, that define m clock domains, wherein m.gtoreq.2 and n.gtoreq.m. A clock driver... |
| US-7,373,567 |
System and method of providing error detection and correction capability
in an integrated circuit using... A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array... |
| US-7,373,566 |
Semiconductor device for accurate measurement of time parameters in
operation A memory-logics LSI device forms an input/output path for testing. A memory device has a memory input/output unit,which includes an input/output selector with... |
| US-7,373,565 |
Start/stop circuit for performance counter A circuit for tracking a number of clock cycles between occurrences of an event of interest. The circuit includes logic for asserting a run signal responsive to... |
| US-7,373,564 |
Semiconductor memory A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular... |
| US-7,373,563 |
Root cause correlation in connectionless networks A method for correlating routing errors to link failures in a network, the method including detecting a link failure between a first and a second router NODES in... |
| US-7,373,562 |
Memory circuit comprising redundant memory areas The invention relates to a memory circuit comprising regular memory areas and redundant memory areas, redundancy circuits in each case being assigned to the... |
| US-7,373,561 |
Integrated packet bit error rate tester for 10G SERDES An integrated packet bit error rate tester includes a packet transmit circuit that has a first memory for storing transmit packet data and is connectable to a... |
| US-7,373,560 |
Circuit for measuring signal delays of asynchronous inputs of synchronous
elements A system measures propagation delays in any number of test circuits, each having two asynchronous inputs and an output, without using their clock inputs to... |
| US-7,373,559 |
Method and system for proactive drive replacement for high availability
storage systems Methods for preventing the failure of disk drives in storage systems are disclosed. A system and a computer program product for preventing the failure are also... |
| US-7,373,558 |
Vectoring process-kill errors to an application program A processor includes a process identifier unit to assign process identifiers to one or more processes executed by the processor. The processor also includes an... |
| US-7,373,557 |
Performance monitor for data processing systems A portable scalable performance monitoring system is provided for monitoring the performance of one or more data processing systems in real time. The portable... |
| US-7,373,556 |
Method for monitoring sub-system health A server self health monitor (SHM) system monitors the health of the server it resides on. The health of a server is determined by the health of all of a... |
| US-7,373,555 |
Systems and methods controlling transaction draining for error recovery Disclosed are systems and methods for controlling transaction draining for error recovery comprising asserting a control signal to prevent system resources... |
| US-7,373,554 |
Techniques for automatic software error diagnostics and correction Techniques are provided for automatically circumventing errors encountered by a software system. The software system automatically determines that the code path... |
| US-7,373,553 |
Computer support network with customer portal to monitor incident-handling
status by vendor's computer service... Customer support personnel can access via a vendor's portal an automated support vendor website to view the status of a fault incident that is being handled by... |
| US-7,373,552 |
Model based diagnosis and repair for event logs A system and appertaining method isolates a hardware or user error in a software controlled apparatus e.g., an NMR-apparatus. A diagnostic function is added to... |
| US-7,373,551 |
Method to provide autonomic boot recovery In some embodiments, the invention involves a system and method relating to autonomic boot recovery. In at least one embodiment, the present invention utilizes... |
| US-7,373,550 |
Generation of a computer program to test for correct operation of a data
processing apparatus Software built in self test computer programs 12 are generated using a genetic algorithm 14 technique. A fault simulator 20 is used to simulate candidate... |
| US-7,373,549 |
Error detection and recovery in a storage driver A command is received, at a network storage driver, from an operating system storage stack, wherein the command is for communication with a target storage device... |
| US-7,373,548 |
Hardware recovery in a multi-threaded architecture Log-based hardware recovery. A checkpointed state of a system includes both architectural register values and memory. The checkpoint consists of a copy of the... |
| US-7,373,547 |
Self-reparable semiconductor and method thereof A self-reparable semiconductor comprises first, second and spare functional units including first and second sub-functional units that cooperate to perform first... |
| US-7,373,546 |
Cluster network with redundant communication paths A cluster network is provided in which the storage enclosures of the network are grouped into storage sets or columns of storage enclosures. Each server node of... |
| US-7,373,545 |
Fault tolerant computer system A fault-tolerant computer system includes at least two servers, each of which is configured to perform a first set of operations. Each of the two servers... |
| US-7,373,544 |
Concept of zero network element mirroring and disaster restoration process There is provided a system and method of disaster restoration of service of damaged or destroyed telecommunication network elements. A controller component is... |
| US-7,373,543 |
Method and apparatus for uninterrupted packet transfer using replication
over disjoint paths A method of operating a fault tolerant connection in a network is described. The network includes a number of network elements and a number of links. Each of the... |
| US-7,373,542 |
Automatic startup of a cluster system after occurrence of a recoverable
error The invention relates to a method for the automatic startup of a cluster (10) after an error has occurred in a node (12, 14) of said cluster (10) that led to a... |
| US-7,373,541 |
Alignment signal control apparatus and method for operating the same Broadly speaking, an apparatus and associated method of operation is provided for controlling alignment signal transmission in an electronic communication... |
| US-7,373,540 |
System-on-chip having adjustable voltage level and method for the same A system-on-chip may include a plurality of power domains each of which may have a different operating frequency and include a monitoring unit. A power supply... |
| US-7,373,539 |
Parallel path alignment method and apparatus A method for aligning parallel path data bit streams that may contain skewed data between bit streams and an integrated circuit are disclosed. The method... |
| US-7,373,538 |
Method for determining interconnect line performance within an integrated
circuit A method for determining propagation delay differences for conductive lines of an integrated circuit is described. A first path is formed by coupling a first... |
| US-7,373,537 |
Response to wake event while a system is in reduced power consumption
state An apparatus adapted to facilitate execution of task or tasks in response to a detection of an occurrence of one of one or more particular wake events while a... |
| US-7,373,536 |
Fine granularity halt instruction Systems and methods for halting the execution of instructions in a microprocessor are disclosed. The halt instruction may have an operand which allows a... |
| US-7,373,535 |
Electric power saving apparatus comprising semi-conductor device to pass
energy of infrared ray synthetic... The present invention relates to an electric power saving apparatus wherein light energy is irradiated to a semiconductor device, with the light energy emitted... |
| US-7,373,534 |
Reducing storage data transfer interference with processor power
management Systems and methods of managing power consumption provide for placing a processor in a non-snoopable state while a storage interface associated with the... |
| US-7,373,533 |
Programmable I/O cell capable of holding its state in power-down mode The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive... |
| US-7,373,532 |
Inline power controller An inline power controller includes at least one analog interface circuit module (AICM) having a first analog input node for receiving an inline power port... |
| US-7,373,531 |
Signal detection method, frequency detection method, power consumption
control method, signal detecting device,... A power consumption control device for detecting output of a pulse signal from an output terminal of an oscillator as an operation monitoring target and... |
| US-7,373,530 |
Systems and methods for providing power-loss protection to sleeping
computers systems Transitioning to a suspend to RAM sleeping state while also protecting against power losses while sleeping is provided. System state context data is saved to... |
| US-7,373,529 |
Performing a power supply check for an information storage device to
increase power consumption in a stepwise... In an information storage device adapted to use a power supply supplied from an interface or a battery, a voltage input from the power supply is monitored in... |
| US-7,373,528 |
Increased power for power over Ethernet applications According to one embodiment of the invention, a method for supplying power over Ethernet includes determining whether a first port of power sourcing equipment is... |
| US-7,373,527 |
System and method for interleaving point-of-load regulators A system and method for providing interleaving point-of-load (POL) regulators such that each regulator's switching cycle is phase displaced with respect to those... |
| US-7,373,526 |
System and method for managing power in an ASF system Techniques are disclosed for providing system manageability for computing systems operating under OS-absent conditions. In particular, techniques are disclosed... |
| US-7,373,525 |
Data processing method and data checking method Cyclic-redundancy-check (CRC) processing is executed on data blocks each having a predetermined data amount, thereby calculating respective CRC values for the... |
| US-7,373,524 |
Methods, systems and computer program products for monitoring user
behavior for a server application Methods, systems and computer program products are disclosed for monitoring user behavior for a server application in a computer network. The methods, systems,... |
| US-7,373,523 |
Preparing data for storage in a secure fashion Digital data is prepared for storage in a secure fashion. Each data byte of a data file is encrypted. A unique bit number is assigned to each data bit in the... |
Copyright 2008−2012 Patents.com
