Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,371,660 |
Controlled cleaving process A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface... |
| US-7,371,659 |
Substrate laser marking A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where... |
| US-7,371,658 |
Trench isolation structure and a method of manufacture therefor The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the... |
| US-7,371,657 |
Method for forming an isolating trench with a dielectric material The present invention relates to a method of forming an isolating trench of a semiconductor device with a dielectric material, and to a method of forming an... |
| US-7,371,656 |
Method for forming STI of semiconductor device A method for forming a STI of a semiconductor device includes steps of sequentially forming a pad oxide film and a pad nitride film on the semiconductor device... |
| US-7,371,655 |
Method of fabricating low-power CMOS device A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an... |
| US-7,371,654 |
Manufacturing method of semiconductor device with filling insulating film
into trench Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an... |
| US-7,371,653 |
Metal interconnection structure of semiconductor device and method of
forming the same Provided is a metal interconnection structure of a semiconductor device, having: a lower metal layer disposed on an insulating layer formed on a semiconductor... |
| US-7,371,652 |
Alignment using fiducial features The present invention relates to positioning components of an assembly using fiducial features. A first fiducial feature on a first piece of the assembly can be... |
| US-7,371,651 |
Flat-type capacitor for integrated circuit and method of manufacturing the
same Embodiments of the invention provide flat-type capacitors that prevent degradation of the dielectric layer, thereby improving the electrical properties of the... |
| US-7,371,650 |
Method for producing a transistor structure A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes... |
| US-7,371,649 |
Method of forming carbon-containing silicon nitride layer A method for forming a carbon-containing silicon nitride layer with superior uniformity by low pressure chemical vapor deposition (LPCVD) using disilane, ammonia... |
| US-7,371,648 |
Method for manufacturing a transistor device having an improved breakdown
voltage and a method for... The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The... |
| US-7,371,647 |
Methods of forming transistors The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of... |
| US-7,371,646 |
Manufacture of insulated gate type field effect transistor After a field insulating film having an element opening is formed on the surface of a p-type well, a gate insulating film is formed on a semiconductor surface in... |
| US-7,371,645 |
Method of manufacturing a field effect transistor device with recessed
channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate... |
| US-7,371,644 |
Semiconductor device and method of fabricating the same According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor... |
| US-7,371,643 |
Nonvolatile semiconductor memory device A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate... |
| US-7,371,642 |
Multi-state NROM device An array of NROM flash memory cells configured to store at least two bits per four F.sup.2. Split vertical channels are generated along each side of adjacent... |
| US-7,371,641 |
Method of making a trench MOSFET with deposited oxide A trench type power semiconductor device which includes deposited rather than grown oxide in the trenches for the electrical isolation of electrodes disposed... |
| US-7,371,640 |
Semiconductor device with floating trap type nonvolatile memory cell and
method for manufacturing the same The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method... |
| US-7,371,639 |
Nonvolatile memory device and method for fabricating the same A nonvolatile memory device and a method for fabricating the same decreases power consumption and prevents contamination of an insulating layer. The nonvolatile... |
| US-7,371,638 |
Nonvolatile memory cells having high control gate coupling ratios using
grooved floating gates and methods of... A non-volatile memory cell includes a semiconductor substrate having a fin-shaped active region extending therefrom. A tunnel dielectric layer is provided, which... |
| US-7,371,637 |
Oxide-nitride stack gate dielectric A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the... |
| US-7,371,636 |
Method for fabricating storage node contact hole of semiconductor device A method for fabricating a storage node contact hole of a semiconductor device includes: forming an inter-layer insulation layer over a substrate; forming a hard... |
| US-7,371,635 |
Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device includes: forming a transistor with first and second ends of a main current path, and a control electrode,... |
| US-7,371,634 |
Amorphous carbon contact film for contact hole etch process A semiconductor device including a contact etch stop layer and contact hole formation method for reduced underlying material loss and improved device... |
| US-7,371,633 |
Dielectric layer for semiconductor device and method of manufacturing the
same A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer... |
| US-7,371,632 |
Semiconductor device having high-voltage transistor and PIP capacitor and
method for fabricating the same A semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a method for fabricating the same are... |
| US-7,371,631 |
Method of manufacturing a nonvolatile semiconductor memory device, and a
nonvolatile semiconductor memory device For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is... |
| US-7,371,630 |
Patterned backside stress engineering for transistor performance
optimization Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance. |
| US-7,371,629 |
N/PMOS saturation current, HCE, and Vt stability by contact etch stop film
modifications A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide... |
| US-7,371,628 |
Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a... |
| US-7,371,627 |
Memory array with ultra-thin etched pillar surround gate access
transistors and buried data/bit lines A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally... |
| US-7,371,626 |
Method for maintaining topographical uniformity of a semiconductor memory
array A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile... |
| US-7,371,625 |
Semiconductor device and manufacturing method thereof, liquid crystal
television system, and EL television system The present invention provides a method for a semiconductor device, which comprises the steps of forming a first conductive layer in contact with a semiconductor... |
| US-7,371,624 |
Method of manufacturing thin film semiconductor device, thin film
semiconductor device, electro-optical device,... A method of manufacturing a thin film semiconductor device which includes a thin film transistor having a first semiconductor layer, a gate insulating layer, and... |
| US-7,371,623 |
Semiconductor device with semiconductor circuit comprising semiconductor
units, and method for fabricating it The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT... |
| US-7,371,622 |
Etchant for signal wire and method of manufacturing thin film transistor
array panel using etchant Gate lines including a lower Al--Nd layer and an upper MoW layer, data lines including a MoW layer, and pixel electrodes including an IZO layer are patterned... |
| US-7,371,621 |
Thin film transistor array panel and fabrication The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate... |
| US-7,371,620 |
Apparatus and method for laser radiation There is provided an improvement on homogeneity of annealing performed utilizing radiation of a laser beam on a silicon film having a large area. In a... |
| US-7,371,618 |
Method of manufacturing wafer-level chip-size package and molding
apparatus used in the method Provided are a method of manufacturing wafer-level chip-size packages and a molding apparatus suitable for practicing the method whereby a semiconductor wafer... |
| US-7,371,617 |
Method for fabricating semiconductor package with heat sink A semiconductor package with a heat sink and a method for fabricating the same are proposed. The heat sink is provided with a rigid and thermally resistant... |
| US-7,371,616 |
Clipless and wireless semiconductor die package and method for making the
same A method for making a semiconductor die package is disclosed. In some embodiments, the method includes using a leadframe structure including at least one lead... |
| US-7,371,615 |
Heat sink and method for its production A method for producing a heat sink for cooling a semiconductor device including forming plural base members, the base member being each in plate or block-shape,... |
| US-7,371,614 |
Image sensor device and methods thereof An image sensor device and methods thereof. In an example method, a protective layer may be formed over at least one microlens. An adhesive layer may be formed... |
| US-7,371,613 |
Semiconductor device and method of manufacturing the same A semiconductor device manufacturing method capable of improving the semiconductor device manufacturing yield is disclosed. Semiconductor chips are mounted... |
| US-7,371,612 |
Method of fabrication of stacked semiconductor devices A method for increasing integrated circuit density is disclosed comprising stacking an upper wafer and a lower wafer, each of which having fabricated circuitry... |
| US-7,371,610 |
Process for fabricating an integrated circuit package with reduced mold
warping A process for fabricating an integrated circuit package includes mounting a semiconductor die on a first surface of a metal carrier and forming electrical... |
| US-7,371,609 |
Stacked module systems and methods The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment... |
Copyright 2008−2012 Patents.com
