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| Patent # | Description |
|---|---|
| US-7,373,472 |
Storage switch asynchronous replication Systems and methods in accordance with embodiments are provided for the replication of data from virtual logical units to remote virtual logical units. Change... |
| US-7,373,471 |
Executing background writes to idle DIMMs Memory modules are designed with multiple write buffers utilized to temporarily hold write data. "Write-to-buffer" operations moves write data from the memory... |
| US-7,373,470 |
Remote copy control in a storage system In a storage system that executes multi-target remote copying, the identity of data across two secondary storage subsystems may be quickly and flexibly ensured.... |
| US-7,373,469 |
Data migration method A first storage system includes a first storage area for storing data written by a computer. A second storage system includes a second storage area to which the... |
| US-7,373,468 |
Control facility for processing in-band control messages during data
replication A control facility that allows a non-programmer to use and manipulate replicated data without disrupting replication of the data itself. The control facility can... |
| US-7,373,467 |
Storage device flow control A method for allocating data write credits for a storage device includes gathering requests for the data write credits from a plurality of data sources and... |
| US-7,373,466 |
Method and apparatus for filtering memory write snoop activity in a
distributed shared memory computer A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include... |
| US-7,373,465 |
Data processing system configuring and transmitting access request frames
with a field in channel command words... In a data processing system in which a host processing apparatus and a storage subsystem are connected via a channel interface, the present invention makes it... |
| US-7,373,464 |
Efficient data storage system A method for storing data comprising is disclosed. The method comprises receiving a data stream comprising a plurality of data segments wherein each data segment... |
| US-7,373,463 |
Antifraud method and circuit for an integrated circuit register containing
data obtained from secret quantities An integrated circuit and an antifraud method implementing at least one operation involving at least one secret quantity, and functionally including upstream and... |
| US-7,373,462 |
Snoop filter for filtering snoop requests A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one... |
| US-7,373,461 |
Speculative directory lookup for sharing classification In one embodiment, a node for a multi-node computer system comprises a coherence directory configured to store coherence states for coherence units in a local... |
| US-7,373,460 |
Media drive and command execution method thereof Embodiments of the present invention provide a media drive capable of improving command processing performance by, when a plurality of commands is queued,... |
| US-7,373,459 |
Congestion control and avoidance method in a data processing system A congestion control and avoidance method including a method check step of determining whether the request contents is cacheable or uncacheable on the basis of... |
| US-7,373,458 |
Cache memory system with multiple ports cache memories capable of
receiving tagged and untagged requests There is described a cache memory system including a first cache memory and a second cache memory. A first port is arranged to receive a request for a first item... |
| US-7,373,457 |
Cache coherence protocol for a multiple bus multiprocessor system A computer system maintains a list of tags (called a Global Ownership Tag List (GOTL)) for all the cache lines in the system that are owned by a cache. The GOTL... |
| US-7,373,456 |
Disk array apparatus and disk array apparatus controlling method Times at which requests for a data read or data write from/to a logical volume are received are stored in memory as access times of a RAID group making up the... |
| US-7,373,455 |
Storage system and storage system control method in which storage areas
can be added as needed Method and apparatus for using the storage resources of a storage system effectively, thereby reducing the cost of the storage system and improving its... |
| US-7,373,454 |
Pattern detect and byte align circuit using CAM A method detects a programmable pattern (e.g., Ethernet comma or SONET A1A2 frame) and simultaneously byte aligns to that pattern. The technique uses a content... |
| US-7,373,453 |
Method and apparatus of interleaving memory bank in multi-layer bus system A method and apparatus of interleaving memory banks in a multi-layer bus system. The apparatus includes a plurality of slave interface units receiving signals... |
| US-7,373,452 |
Controller for controlling nonvolatile memory A memory controller is provided which is connected to a nonvolatile memory (e.g., a NAND flash memory) and a volatile memory (e.g., a DRAM or SDRAM), where the... |
| US-7,373,451 |
Cache-based system management architecture with virtual appliances,
network repositories, and virtual appliance... A cache-based system management architecture named "the Collective" automates system management and supports mobile computing. The Collective manages systems by... |
| US-7,373,450 |
Multi-layer bus system having a bus control circuit A multi-layer bus system includes an interconnect matrix, bus slaves, bus masters and a bus control circuit. The interconnect matrix has master connection ports... |
| US-7,373,449 |
Apparatus and method for communicating in an integrated circuit An integrated circuit comprising a plurality of processing modules (M; I; S; T) and a network (N; RN) arranged for providing at least one connection between a... |
| US-7,373,448 |
Method, system, and program for building a queue to test a device Provided are a method, system, and device for signaling a reconnection inhibitor over a bus to cause the reconnection inhibitor to access the bus to inhibit an... |
| US-7,373,447 |
Multi-port processor architecture with bidirectional interfaces between
busses A multi-port processor architecture having a first bus, a second bus and a central processing unit. The central processing unit having a first and second ports... |
| US-7,373,446 |
Method and system for dynamically patching an operating system's interrupt
mechanism In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture... |
| US-7,373,445 |
Method and apparatus for allocating bus access rights in multimaster bus
systems A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device... |
| US-7,373,444 |
Systems and methods for manipulating entries in a command buffer using tag
information Systems and methods for facilitating the location of entries in a buffer where a slave device stores information related to an active transaction so that the... |
| US-7,373,443 |
Multiple interfaces in a storage enclosure Provided is a method for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and... |
| US-7,373,442 |
Method for using an expander to connect to different storage interconnect
architectures Provided is a system for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and... |
| US-7,373,440 |
Switch/network adapter port for clustered computers employing a chain of
multi-adaptive processors in a dual... A switch/network adapter port ("SNAP") for clustered computers employing multi-adaptive processor ("MAP.TM.", a trademark of SRC Computers, Inc.) elements in a... |
| US-7,373,439 |
System method using material exchange format (MXF) converting program for
audio and video data files having... An MXF parser thread 43 parses data MXF_D, being, mixed together, a plurality of video data PIC, a plurality of audio data SOU, and system data SYS. Then, it... |
| US-7,373,438 |
System and method for reprioritizing high-latency input/output operations A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the... |
| US-7,373,437 |
Multi-channel DMA with shared FIFO A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with "m" threads... |
| US-7,373,436 |
Storage control device and method for management of storage control device A storage control device, connected to a host processing device through a full-duplex channel and for storing data received through the channel in a data storage... |
| US-7,373,435 |
Extended input/output measurement block An Input/output (I/O) measurement block facility is provided that creates subchannel measurement blocks (comprising device busy values) related to performance of... |
| US-7,373,434 |
Multi-function apparatus and control method thereof A multi-function apparatus having a wider variety of uses and easily employed when carrying a USB cable only without having a power source cord. The apparatus... |
| US-7,373,433 |
Apparatus and method to provide failover protection in an information
storage and retrieval system A method is disclosed for failover protection in an information storage and retrieval system comprising two clusters, two device adapters, and a plurality of... |
| US-7,373,432 |
Programmable circuit and related computing machine and method A programmable circuit receives configuration data from an external source, stores the firmware in a memory, and then downloads the firmware from the memory.... |
| US-7,373,431 |
Signal processing apparatus, signal processing method, signal processing
system, program and medium Changes to the functionality and the detection and an expansion of a signal processing apparatus that processes an input signal are disclosed. A first signal... |
| US-7,373,430 |
Cluster accelerator network interface with filter An apparatus for improving communication between network devices in a cluster. is provided. A filter is used to pre-process packets to determine if they need to... |
| US-7,373,429 |
Integrated IP network To provide an integrated IP network containing therein a plurality of separated IP networks with a variety of characteristics, such as IP telephone network, IP... |
| US-7,373,428 |
Intelligent filtering for contact spanning multiple access networks A personal communications portal maintains presence information about a user who may be available at one or more terminal devices on one or more access networks... |
| US-7,373,426 |
Network system using name server with pseudo host name and pseudo IP
address generation function The host name to be used in responding to the reverse look-up request from the correspondent is generated at the name server side and returned as a response,... |
| US-7,373,425 |
High-speed MAC address search engine Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a... |
| US-7,373,424 |
Exactly once protocol for message-based collaboration Methods and systems for reliably exchanging a message among collaborating applications are disclosed. The methods and systems utilize a central exchange... |
| US-7,373,423 |
Network infrastructure management and data routing framework and method
thereof The invention generally provides a method for routing data into and out of a network having a plurality of host computers corresponding to a plurality of network... |
| US-7,373,422 |
Techniques for supporting multiple devices in mobile applications Techniques for interacting with a client process on a mobile device connected to a network over a wireless link includes managing information at a mobile... |
| US-7,373,421 |
Method and apparatus of preventing physical layer from establishing
unsupported links Methods and apparatus for preventing unsupported links between a host device and a link partner over a network is disclosed. In one embodiment, a link control... |
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