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| Patent # | Description |
|---|---|
| US-7,409,672 |
Method and apparatus for communicating information between a browser and
an application program A method and apparatus are provided for communicating information and carrying out other interactions between a browser and an application program. A hyperaction... |
| US-7,409,671 |
Model for business workflow processes A methodology of reducing process algebra to a language that facilitates modeling a business workflow process is provided. A process algebra is reduced to a... |
| US-7,409,670 |
Scheduling logic on a programmable device implemented using a high-level
language Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as... |
| US-7,409,669 |
Automatic test configuration generation facilitating repair of
programmable circuits Techniques are provided that control the generation of test routes to improve the ability of a test system to isolate defects on programmable circuits. A test... |
| US-7,409,668 |
Method for improving via's impedance A method is for controlling an impedance of a via of a printed circuit board. The Via is connected with a trace and includes a drill hole, a pad and an anti-pad.... |
| US-7,409,667 |
Techniques for modeling a circuit board structure A technique generates circuit board modeling data for a circuit board structure having multiple layers. The technique includes receiving a set of global circuit... |
| US-7,409,666 |
Automated PCB manufacturing documentation release package system and
method An automated PCB manufacturing documentation release package system including a PCB database including PCB CAD data associated with a CAD file of a PCB design,... |
| US-7,409,665 |
Method for checking return path of printed and CAD apparatus for designing
patterns of printed board A CAD apparatus designing patterns of a printed board. The apparatus includes a signal wiring pattern detecting unit for detecting a signal wiring pattern, and a... |
| US-7,409,664 |
Architecture and interconnect scheme for programmable logic circuits An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide... |
| US-7,409,663 |
Process for the production of an electrical wiring diagram This process allows for the automatic production of an electrical wiring diagram on which are located boxes, each representing a component used in an electrical... |
| US-7,409,662 |
Systems and methods involving designing shielding profiles for integrated
circuits A method for designing shielding in integrated circuits, the method comprising, receiving a first input designating a first net segment profile on a first level... |
| US-7,409,661 |
Computer-aided thermal relief pad design system and method A computer-aided thermal relief pad design system includes a depicting unit, a memory unit and a calculating unit. The depicting unit is used for depicting an... |
| US-7,409,660 |
Method and end cell library for avoiding substrate noise in an integrated
circuit A method of avoiding substrate noise in an integrated circuit includes steps of receiving as input an integrated circuit design that includes at least a portion... |
| US-7,409,659 |
System and method for suppressing crosstalk glitch in digital circuits A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net,... |
| US-7,409,658 |
Methods and systems for mixed-mode physical synthesis in electronic design
automation Methods and systems for electronic design automation includes clustering objects into more manageable numbers of objects. Clustering is optionally performed to... |
| US-7,409,657 |
Clock tree layout method for semiconductor integrated circuit By executing the steps of sequentially retrieving buffers on a clock tree from a clock source to input pins of the cells other than the buffers and recognizing... |
| US-7,409,656 |
Method and system for parallelizing computing operations Disclosed is an improved method and system for implementing parallel processing of computing operations by effectively handling dependencies between different... |
| US-7,409,655 |
Method of designing semiconductor integrated circuit and apparatus for
designing the same A method of designing a semiconductor integrated circuit having a plurality of transistors calculates a leak current corresponding to a sum of a gate leak and a... |
| US-7,409,654 |
Method and apparatus for performing test pattern autograding A method, computer program product, and data processing system for minimizing the number of test sequences needed to achieve a desired level of coverage of... |
| US-7,409,653 |
Sub-resolution alignment of images A plurality of images, including a first image and a second image having a higher resolution than the first image, are aligned by generating an oversampled cross... |
| US-7,409,652 |
Debuggable opaque IP Partially opaque intellectual property (IP) includes source code providing the IP functionality. Meta-comments (pragmas or attributes) are provided with the... |
| US-7,409,651 |
Automated migration of analog and mixed-signal VLSI design A method for migrating an electronic circuit from a source technology to a target technology includes accepting a source circuit that operates in the source... |
| US-7,409,650 |
Low power consumption designing method of semiconductor integrated circuit In a standard cell synthesizing step 101, a net list is synthesized from an RTL description, and an instance name list is formed which contrasts a register... |
| US-7,409,649 |
System and method for automatically calculating parameters of an MOSFET A system for automatically calculating parameters of an MOSFET is disclosed. The parameter calculating system runs in a computer. The parameter calculating... |
| US-7,409,648 |
Semiconductor integrated circuit, method for designing semiconductor
integrated circuit and system for... The semiconductor integrated circuit capable of reducing an interconnection width as compared with conventional one while suppressing electromigration... |
| US-7,409,647 |
Control of interactions within virtual environments A virtual object for use in an object oriented environment; the virtual object comprising at least a user-sensible aspect and further comprising at least a... |
| US-7,409,646 |
System and method for manipulating toolbar component dimensions A system and method for manipulating toolbar dimensions are provided. Each toolbar includes a number of toolbar components having a textual representation and a... |
| US-7,409,645 |
User interface and operating system for presenting the contents of a
content collection based on content type An apparatus and method for execution in a graphical user interface environment are provided. The apparatus and method are used to display a set of items within... |
| US-7,409,644 |
File system shell A file system shell is provided. One aspect of the shell provides virtual folders which expose regular files and folders to users in different views based on... |
| US-7,409,643 |
Graphical user interface for travel planning system A graphical user interface for a travel planning system is described. The graphical user interface is implemented as a web page and includes a tabular region of... |
| US-7,409,642 |
Method and system for applying user interface elements to data Systems and methods for providing and associating or combining visual style information with data content. The present invention relates to associating a shared... |
| US-7,409,641 |
Method for replying to related messages A method is provided which utilizes a threading service to offer enhanced features for a document management system including an email system. Various enhanced... |
| US-7,409,640 |
Electronic service manual for product constituted by electric or
electronic circuit A technique for performing an information search relate to parts included in a circuit diagram or a board diagram displayed on a display screen. Network... |
| US-7,409,639 |
Intelligent collaborative media The present invention includes a system and method for enhancing multimedia information shared on electronic systems. The electronic systems are capable of... |
| US-7,409,638 |
Web interface for providing system-status on-demand An Internet web application interfaces to a machine to give users information about the status of the machine. The information on the status of the machine is... |
| US-7,409,637 |
Least-effort variable-length text replacement A computer-implemented method of processing text. A method includes providing a unit of text to a text buffer. The unit of text is divided into one or more shift... |
| US-7,409,636 |
Lightweight application program interface (API) for extensible markup
language (XML) An architecture that leverages support for markup language operations, e.g., extensible markup language (XML) queries, via a lightweight application program... |
| US-7,409,635 |
Display/layout methods and apparatuses including content items and display
containers Methods and apparatuses for generating rendering layout specifications for content items to be rendered, using display containers, and/or rendering the content... |
| US-7,409,634 |
Method and apparatus for end-to-end content publishing system using XML
with an object dependency graph The system for end-to-end content publishing using XML with an object dependency graph is based on the following two design principles: First, separation of... |
| US-7,409,633 |
System and method for annotating web-based document Computer users may integrate any annotation, including ink, highlighter, text-based notes and audio, directly into a Web-based document (WBD) displayed by a Web... |
| US-7,409,632 |
Classifying, disabling and transmitting form fields in response to data
entry An attachment integrated claims (AIC) system includes an e-mail form (with specific fields that must be filled out) that adjusts itself, in both information... |
| US-7,409,631 |
Error-detection flip-flop An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including... |
| US-7,409,630 |
Modified chase combining for hybrid automatic repeat request Error correction techniques based on a modified chase combining (MCC) in data retransmission in communication systems such as wired and wireless communication... |
| US-7,409,629 |
Methods and devices for decoding one-point algebraic geometric codes A method of decoding a one-point algebraic geometric code of dimension k and length n, in which, in order to identify the position of the errors in a received... |
| US-7,409,628 |
Efficient design to implement LDPC (Low Density Parity Check) decoder Efficient design to implement LDPC decoder. The efficient design presented herein provides for a solution that is much easier, smaller, and has less complexity... |
| US-7,409,627 |
Method for transmitting and receiving variable length packets based on
forward error correction (FEC) coding A method for transmitting variable length packets based on FEC coding. Data packets are successively and contiguously stored in a two-dimensional storage device.... |
| US-7,409,626 |
Method and apparatus for determining codeword interleaver parameters Modem selection of codeword interleaver parameters given standard based, operator based and channel based communication channel performance constraints. A... |
| US-7,409,625 |
Row-diagonal parity technique for enabling efficient recovery from double
failures in a storage array A method for enabling recovery from concurrent failure of a plurality of storage devices in a storage array is disclosed. The method stores data on a first... |
| US-7,409,624 |
Memory command unit throttle and error recovery A network device for minimizing latency and correcting errors associated with information transmitted from an external memory device. The network device includes... |
| US-7,409,623 |
System and method of reading non-volatile computer memory The disclosure is directed to a method of reading a portion of a non-volatile computer memory including reading a first portion of a redundant memory area of a... |
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