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| Patent # | Description |
|---|---|
| US-7,409,622 |
System and method for reverse error correction coding A system and method for Reverse Error Correction Coding. The system includes a Constraint encoder, an Error Correction Code encoder, and a uniform interleaver.... |
| US-7,409,621 |
On-chip jitter testing On-chip jitter testing includes providing a clock signal to a circuit under test and delaying outputs from the circuit under test by predetermined delay values.... |
| US-7,409,620 |
Simplified high speed test system A method for configuring a testing system that includes a step of connecting a commercially available computer (CACMP) for directly controlling transmission of a... |
| US-7,409,619 |
System and methods for authoring domain specific rule-driven data
generators An automated data generation system and methods are provided to facilitate generation of test data sets for computerized platforms while mitigating the need to... |
| US-7,409,618 |
Self verifying communications testing A system and method for testing a device with multiple interfaces by generating a predetermined data pattern within the device, transmitting the pattern to a... |
| US-7,409,617 |
System for measuring characteristics of a digital signal An electronic device under test (DUT) responds to a digital input signal by generating a digital DUT output signal conveying a repetitive digital signal pattern.... |
| US-7,409,616 |
Built in self test system and method for detecting and correcting cycle
slip within a deserializer A system and method are provided for built-in-self test of any bits that have slipped from their appropriate positions within a frame character clock cycle. If a... |
| US-7,409,615 |
Test apparatus and test method A test apparatus for testing a device under test 15 is provided. The test apparatus includes a driver 122 for applying a test signal to the device under test, a... |
| US-7,409,614 |
Method, system and program product for boundary I/O testing employing a
logic built-in self-test of an... A testing method is provided which includes verifying at least one external signal path of an electronic package environment by testing an input/output (I/O)... |
| US-7,409,613 |
Simultaneous AC logic self-test of multiple clock domains A technique is provided for simultaneous and/or selective self-testing of internal logic and asynchronous boundaries of an IC having a plurality of clock... |
| US-7,409,612 |
Testing of integrated circuits An integrated circuit with a test interface contains a boundary scan chain with cells (14) coupled between a test data input (TDI) and output (TDO) in a shift... |
| US-7,409,611 |
Wrapper instruction/data register controls from test access or wrapper
ports In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture,... |
| US-7,409,610 |
Total configuration memory cell validation built in self test (BIST)
circuit A built in self test (BIST) circuit is provided for a programmable logic device (PLD) constructed from fixed or hard core logic that includes circuitry to write... |
| US-7,409,609 |
Integrated circuit with a control input that can be disabled An integrated circuit comprises a control unit, a plurality of control inputs for the provision of control signals to said control unit and a deactivation... |
| US-7,409,608 |
Pseudo-random wait-state and pseudo-random latency components Methods and apparatus are provided for testing logic, particularly arbitration logic on a programmable chip. Secondary components on a programmable chip are... |
| US-7,409,607 |
Memory address generating apparatus, processor having the same, and memory
address generating method A memory address generating apparatus comprising an address converting circuit, after setting a first setting region storing substitution source data and a... |
| US-7,409,606 |
Method and system for interleaving in a parallel turbo decoder A method and system for interleaving in a parallel turbo decoder enables the use of economical dual-port memory. According to the method, an incoming coding... |
| US-7,409,605 |
Storage system The failure management sections of a host computer and a storage unit are connected through a failure reporting interface. When a failure occurs in the storage... |
| US-7,409,604 |
Determination of related failure events in a multi-node system Systems and methods for determining related node failures in a multi-node system use log data obtained from the nodes. This log data is processed in various ways... |
| US-7,409,603 |
System and method for testing hardware devices A system for testing hardware devices applies a multi-level architecture including a Graphical User Interface (GUI) level (10), a Dynamic Link Library (DLL)... |
| US-7,409,602 |
Methodology for debugging RTL simulations of processor based system on
chip An apparatus comprising an analysis block, a graphic user interface and a memory circuit. The analysis block may be configured to generate debug information in... |
| US-7,409,601 |
Read-write function separation apparatus and method A system and method for a software override capability for enforcing a predetermined state for an otherwise hardware-programmable device. Software that may think... |
| US-7,409,600 |
Self-healing cache system A method, apparatus and program storage device for performing a self-healing cache process is described. At least one error affecting a cache is detected. The... |
| US-7,409,599 |
Method of verifying defect management area information of optical disc
upon initialization without... A method of verifying defect management area (DMA) information of an optical disc upon initialization without certification, and a test apparatus for performing... |
| US-7,409,598 |
Information storage system A host device 1 includes an NG table 10 for storing addresses specifying areas of a bulk memory 3 into which data cannot be written, a performance-guaranteed... |
| US-7,409,597 |
Processor bus for performance monitoring with digests A method for monitoring event occurrences from a plurality of processor units at a centralized location via a dedicated bus coupled between the plurality of... |
| US-7,409,596 |
Apparatus and method for initializing diagnostic functions when specified
run-time error criteria are satisfied A run-time monitor allows defining sets of run-time error criteria and corresponding diagnostic action to take when the run-time error criteria is satisfied. One... |
| US-7,409,595 |
History-based prioritizing of suspected components A method for servicing a computerized system includes detecting a failure of a given type in the computerized system, and generating a list of corrective actions... |
| US-7,409,594 |
System and method to detect errors and predict potential failures A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor... |
| US-7,409,593 |
Automated diagnosis for computer networks Systems for providing automated diagnosis of problems for an electronic network include a central diagnosis engine configured to include modules that rank... |
| US-7,409,592 |
System for facilitating coverage feedback testcase generation
reproducibility An exemplary embodiment of the invention relates to a system for facilitating coverage feedback testcase generation reproducibility. The system comprises a... |
| US-7,409,591 |
Method and system for managing programs for web service system A program managing method in a web service system for providing a web service for testing a message which has been changed in response to a change made in... |
| US-7,409,590 |
Protection against data corruption due to power failure in solid-state
memory device A data preservation system for flash memory systems with a host system, the flash memory system receiving a host system power supply and energizing an auxiliary... |
| US-7,409,589 |
Method and apparatus for reducing number of cycles required to checkpoint
instructions in a multi-threaded... A method and apparatus are provided for reducing the number of cycles required to checkpoint instructions in a multi-threaded microprocessor that has dispatch... |
| US-7,409,588 |
Method and system for data processing with high availability A server to be changed is added to a destination unit in terms of configuration. The server to be changed is started to restore the database in the database... |
| US-7,409,587 |
Recovering from storage transaction failures using checkpoints The disclosed technology facilitates recovery from storage-related failures by checkpointing copy-on-write operation sequences. An operation sequence... |
| US-7,409,586 |
System and method for handling a storage resource error condition based on
priority information Various embodiments of systems and methods are disclosed for using priority information when handling error conditions for a storage resource. In some... |
| US-7,409,585 |
Automatic media repair after read failure due to media error A system and method are provided for a storage device that performs automatic media repair so that, after a media error is encountered, subsequent write... |
| US-7,409,584 |
Automated recovery of computer appliances Aspects of the invention provide methods and architectures for enhancing the reliability of computer appliances and reducing the possibilities that human... |
| US-7,409,583 |
Volume and failure management method on a network having a storage device A SAN manager acquires configuration information from devices constituting a SAN and produces a corresponding relationship between a host computer and a virtual... |
| US-7,409,582 |
Low cost raid with seamless disk failure recovery A storage subsystem such as an array of disk drives, method of managing disk drives in the storage subsystem and program product therefor. The storage subsystem... |
| US-7,409,581 |
Main memory controller adapted to correct corrupted data by xoring
corrupted data to directly generate correct data A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in... |
| US-7,409,580 |
System and method for recovering from errors in a data processing system A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more... |
| US-7,409,579 |
Disk array device having point value added or subtracted for determining
whether device is degraded A trouble case point update unit subtracts point from point stored in a trouble point storage unit when a trouble occurs. A processing-time-reference exceeding... |
| US-7,409,578 |
Graceful load fail over Systems and methodologies that facilitate real time recognition of missing and/or invalid objects in a component based framework, via employing a graceful load... |
| US-7,409,577 |
Fault-tolerant networks Recovery systems and methods for sustaining the operation of a plurality of networked computers (20a, 20b) in the event of a fault conditions are described. The... |
| US-7,409,576 |
High-availability cluster with proactive maintenance One embodiment disclosed relates to a method of preventative maintenance of a high-availability cluster. A least-recently-tested active node is determined. The... |
| US-7,409,575 |
Recovery of computer systems Techniques for enabling remote recovery of computer system is disclosed. OOB communication with a provisioning server is established using a wireless... |
| US-7,409,574 |
Measuring elapsed time for a software routine A method for determining if a measurement of an elapsed time for an execution of a software routine in a computer system is valid. A clock skew is used between... |
| US-7,409,573 |
Micro-controller having USB control unit, MC unit and oscillating circuit
commonly used by the USB control unit... A micro-controller includes a USB control unit, an MC unit having an operation mode and a stop mode and an oscillating circuit, which is commonly used by the USB... |
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