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| Patent # | Description |
|---|---|
| US-7,471,573 |
Integrated circuit device and electronic instrument An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has... |
| US-7,471,572 |
System and method for enhancing erase performance in a CMOS compatible
EEPROM device A system and method are disclosed for enhancing the performance of erase operations in CMOS compatible EEPROM memory cells. An EEPROM memory cell is described in... |
| US-7,471,571 |
Method for programming a memory device suitable to minimize the lateral
coupling effects between memory cells A method programs a memory device that includes at least one memory cell matrix. The programming method the steps of: erasing the memory cells; soft programming... |
| US-7,471,570 |
Embedded EEPROM array techniques for higher density An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM... |
| US-7,471,569 |
Memory having parity error correction A memory includes a sense amplifier segment and a plurality of word lines including a first transfer word line and a second transfer word line complementary to... |
| US-7,471,568 |
Multi-level cell memory structures with enlarged second bit operation
window Multi-level cell memory devices comprise a charge trapping structure with an enlarged second bit operation window formed by hole injection through a gate... |
| US-7,471,567 |
Method for source bias all bit line sensing in non-volatile storage Bit line-to-bit line noise is discharged in a NAND string prior to sensing a programming condition of a selected non-volatile storage element in the NAND string.... |
| US-7,471,566 |
Self-boosting system for flash memory cells A low voltage of the order of or one to three volts instead of an intermediate V.sub.PASS voltage (e.g. of the order of five to ten volts) is applied to word... |
| US-7,471,565 |
Reducing effects of program disturb in a memory device A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on... |
| US-7,471,564 |
Trapping storage flash memory cell structure with inversion source and
drain regions Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in... |
| US-7,471,563 |
Semiconductor memory device Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type... |
| US-7,471,562 |
Method and apparatus for accessing nonvolatile memory with read error by
changing read reference The read reference of a nonvolatile memory integrated circuit is changed in response to a disagreement between a previously generated check code associated with... |
| US-7,471,561 |
Method for preventing memory from generating leakage current and memory
thereof A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The... |
| US-7,471,560 |
Electronic device including a memory array and conductive lines An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can... |
| US-7,471,559 |
Semiconductor memory device for storing multilevel data In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold... |
| US-7,471,558 |
Semiconductor storage device A semiconductor storage device comprising: unit blocks each including memory cells, first row of sense amplifiers on one side of bit lines; second row of sense... |
| US-7,471,557 |
Reading phase change memories to reduce read disturbs Read disturbs in phase change memories may be reduced by progressively reducing the read pulse falling edges. This may reduce the possibility of quenching and... |
| US-7,471,556 |
Local bank write buffers for accelerating a phase-change memory Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory... |
| US-7,471,555 |
Thermally insulated phase change memory device A thermally insulated memory device includes a memory cell, the memory cell having electrodes with a via extending therebetween, a thermal insulator within the... |
| US-7,471,554 |
Phase change memory latch A non-volatile memory latch may be formed with a phase change memory layer. Such a latch may be faster and more easily integrated into main stream semiconductor... |
| US-7,471,553 |
Phase change memory device and program method thereof A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during... |
| US-7,471,552 |
Analog phase change memory An analog memory may be formed using a phase change material. The phase change material may assume one of a number of resistance states which defines a specific... |
| US-7,471,551 |
Magnetic memory The direction of magnetization of a reading ferromagnetic material 5.sub.R forming a spin filter when reading is the same as that of a pinned layer 1. In this... |
| US-7,471,550 |
Magnetic memory A magnetoresistance effect element is also located between second wiring and common wiring. The magnetoresistance effect element is electrically connected to the... |
| US-7,471,549 |
Semiconductor memory device A semiconductor memory device includes a write line, at least three first data-writing circuits which are connected to the write line, and memory cells which... |
| US-7,471,548 |
Structure of static random access memory with stress engineering for
stability An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet... |
| US-7,471,547 |
Memory cell array A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first... |
| US-7,471,546 |
Hierarchical six-transistor SRAM An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing six devices, the storage nodes which store the... |
| US-7,471,545 |
Semiconductor memory device Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory... |
| US-7,471,544 |
Method and apparatus for avoiding cell data destruction caused by SRAM
cell instability Disclosed are embodiments of a method and apparatus for avoiding cell data destruction caused by cell stability problems in static random access memory (SRAM)... |
| US-7,471,543 |
Storage device and semiconductor device A storage device includes a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low... |
| US-7,471,542 |
Information storage apparatus storing and reading information by
irradiating a storage medium with electron beam To greatly increase the storage density of a storage apparatus, an electron beam E emitted from a cold cathode 101 is accelerated by an accelerating electrode... |
| US-7,471,541 |
Memory transistor gate oxide stress release and improved reliability Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory... |
| US-7,471,540 |
Non-volatile semiconductor memory based on enhanced gate oxide breakdown A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during... |
| US-7,471,539 |
High current interconnect structure for IC memory device programming A method and system for a high current semiconductor memory cell provides a semiconductor memory cell with two current carrying structures. At least one of the... |
| US-7,471,538 |
Memory module, system and method of making same A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices... |
| US-7,471,537 |
Content addressable memories (CAM) having low power dynamic match line
sensing circuits therein A content addressable memory array includes a plurality of rows of active CAM cells electrically coupled to a corresponding plurality of active match lines and... |
| US-7,471,536 |
Match mismatch emulation scheme for an addressed location in a CAM A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are... |
| US-7,471,535 |
Programable identification circuitry An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate... |
| US-7,471,534 |
Inverter type motor drive unit An inverter type drive unit for feeding AC electric power of variable parameters to an electric motor has an electronic control section, and a power converting... |
| US-7,471,533 |
DC-to-DC converter with improved transient response A DC to DC converter having improved transient response, accuracy, and stability. The DC to DC converter includes a comparator configured to compare a reference... |
| US-7,471,532 |
Electric circuit, in particular for a medium-voltage power converter Disclosed is an electric circuit, in particular for a medium voltage power converter. The circuit has at least four semiconductor switches which form a series... |
| US-7,471,531 |
Programmable feedback voltage pulse sampling for switched power supplies Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a... |
| US-7,471,530 |
Method and apparatus to reduce audio frequencies in a switching power
supply An apparatus and method of switching a switch of a power supply are disclosed. According to aspects of the present invention, a method includes controlling a... |
| US-7,471,529 |
Universal three phase controllers for power converters The systems and methods described herein provide for a universal controller capable of controlling multiple types of three phase, two and three level power... |
| US-7,471,528 |
Parallel operating system of DC-AC converters and controller IC therefor A multiplicity of synchronized inverters for driving a multiplicity of loads such as CCFLs that require high ac voltages are arranged in close proximity of the... |
| US-7,471,527 |
Green switch power supply with standby function and its IC A switch power supply with standby function is disclosed. The power supply can satisfy the need of the green environment protection. And a single ended green... |
| US-7,471,526 |
Method and apparatus to reduce PWM voltage distortion in electric drives Methods and apparatus are provided for reducing voltage distortion effects at low speed operation in electric drives. The method comprises receiving a first... |
| US-7,471,525 |
Converter and power converter that becomes it with the converter A converter includes a converter circuit 1 having a plurality of bridge-connected semiconductor switching devices for converting AC power into DC power, a... |
| US-7,471,524 |
Isolated DC-DC converters with high current capability A DC-to-DC converter having a transformer with a primary and a tapped secondary, two serial output filter inductors connected parallel with the secondary, a... |
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