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Patent # Description
US-7,472,327 Pattern generator and test apparatus
A pattern generator includes a main memory for storing a plurality of sequence data blocks for generating a test pattern, a first sequence cache memory for...
US-7,472,326 Semiconductor test system having multitasking algorithmic pattern generator
A tester and method are provided for testing semiconductor devices. Generally, the tester includes a multitasking Algorithmic Pattern Generator (APG) to...
US-7,472,325 Method for segmenting BIST functionality in an embedded memory array into remote lower-speed executable...
Disclosed is a method for segmenting functionality of a hybrid built-in self test (BIST) architecture for embedded memory arrays into remote lower-speed...
US-7,472,324 Logic built-in self-test channel skipping during functional scan operations
A method and system for built-in self-testing architecture, including: a logic built-in self-test (LBIST) controller in operable communication with a...
US-7,472,323 Mechanism to stop instruction execution at a microprocessor
A method and apparatus for stopping the internal clock of a microprocessor synchronously with the execution of an instruction is provided. A stop instruction is...
US-7,472,322 On-chip interface trap characterization and monitoring
A method and apparatus for testing semiconductor wafers is disclosed in which a test circuit is used that includes a waveform generator. The test circuit can...
US-7,472,321 Test apparatus for mixed-signal semiconductor device
A test apparatus for a mixed-signal semiconductor device that includes a plurality of event tester modules including analog and digital signal tester boards, a...
US-7,472,320 Autonomous self-monitoring and corrective operation of an integrated circuit
Disclosed is a method and apparatus for autonomously self-monitoring and self-adjusting the operation of an integrated circuit device throughout the integrated...
US-7,472,319 Remote control signal receiver and remote control signal receiving method
A remote control signal receiver receives a remote control signal in which bit signals are included as pulse signals. The remote control signal receiver includes...
US-7,472,318 System and method for determining on-chip bit error rate (BER) in a communication system
A method and system for evaluating performance of a device by on-chip determination of BER may include establishing and generating PRBS test packets in a closed...
US-7,472,317 Coding system and decoding system
In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the...
US-7,472,316 Coding system and decoding system
In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the...
US-7,472,315 Method of seamlessly integrating thermal event information data with performance monitor data
An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the...
US-7,472,314 System and method for monitoring link delays and faults in an IP network
A system for, and method of, monitoring link delays and faults in an IP network. In one embodiment, the system includes: (1) a monitoring station identifier that...
US-7,472,313 Primary server and backup server that share an IP address and a limited number of message identifiers
A primary server and a backup server that both run a RADIUS client in a cold start configuration share a single IP address that includes a limited number of...
US-7,472,312 Invalidation of storage control unit cache metadata
Method, apparatus and program product are provided for rebuilding faulty metadata in a storage controller coupled to a host device. Faulty metadata may include...
US-7,472,311 Method and apparatus for testing an interface between a TCP offload engine and an operating system
One embodiment of the present invention provides a system that can test an interface between a TCP (Transmission Control Protocol) Offload Engine (TOE) and an OS...
US-7,472,310 Debugging mechanism and debugging register
The present invention aims at providing a debugging mechanism capable of detecting erroneous read access to a bus slave caused by a synchronization control...
US-7,472,309 Methods and apparatus to write a file to a nonvolatile memory
A method and apparatus to write a file to a nonvolatile memory is provided. The method may include writing a file to a nonvolatile memory using at least two...
US-7,472,308 Storage switch system, storage switch method, management server, management method, and management program
When a failure is detected in a server currently being used, a management server changes the network topology for the server currently being used and another...
US-7,472,307 Recovery operations in storage networks
Exemplary storage network architectures, data architectures, and methods for creating and using snapdifference files in storage networks are described. One...
US-7,472,306 Processor timing apparatus, systems, and methods
An apparatus and a system, as well as a method and article, may operate to independently adjust a plurality of processor clocks coupled to a corresponding...
US-7,472,305 Method and apparatus for limiting the output frequency of an on-chip clock generator
Apparatus for limiting an output signal frequency of an on-chip clock generator is presented. Electronic circuitry compares the value of a ratio between the...
US-7,472,304 Double data rate system
An extendible timing architecture for an integrated circuit is disclosed. The extendible timing architecture provides metal programmable components for use with...
US-7,472,303 Information preservation on a portable electronic device
A system and method for information preservation on a portable electronic device. A signal indicating an energy capacity threshold remaining in the battery of a...
US-7,472,302 Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay
An adaptive cache decay technique is disclosed that removes power from cache lines that have not been accessed for a variable time interval, referred to as the...
US-7,472,301 Circuitry for optimization of power consumption in a system employing multiple electronic components, one of...
Circuitry for conserving power in a system employing multiple electronic components of which a first electronic component operates at a first frequency and is...
US-7,472,300 Server-managed power saving policies for automated tape libraries and drives
A method of controlling tape drives within a tape drive library where a backup server utilizes client backup schedules and pending client restore requests to...
US-7,472,299 Low power arbiters in interconnection routers
Methods and apparatus to reduce power consumption in arbiters of interconnection routers are described. In one embodiment, an arbiter may be turned off for a...
US-7,472,298 Storage system and method for saving energy based on storage classes with corresponding power saving policies
An example of the invention classifies disks drives based on their purpose and associating power-saving policies in multiple classes. The system implements Power...
US-7,472,297 Method initializing an environment of an integrated circuit according to information stored within the...
A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so...
US-7,472,296 Integrated circuit, semiconductor device and ID chip
A contactless semiconductor device is provided where a low power consumption is achieved and wireless communication is carried out stably. A power supply level...
US-7,472,295 Pre-emptive power supply control system and method
A power supply supplies an output current to an integrated circuit having at least one circuit block. The at least one circuit block has an operating mode...
US-7,472,294 Pre-emptive power supply control system and method
A device comprising an integrated circuit including at least one circuit block having an operating mode controlled in response to an enable signal or a clock...
US-7,472,293 Network processor power management
A programmable state machine is incorporated into the core of a network processor (NP) to monitor the utilization of different processing elements in the NP and...
US-7,472,292 System and method for throttling memory power consumption based on status of cover switch of a computer system
A power throttling method and system for a memory controller in a computer system. One embodiment includes, responsive to a determination that a change in the...
US-7,472,291 Method and apparatus for integrating ACPI functionality and power button functionality into a single power key
A power-managing key apparatus uses a power key to integrate the function of ACPI management of computer hardware and hibernation on/off of operation system. A...
US-7,472,290 Methods and apparatus to maintain and utilize mobile power profile information
A controller in PSE (Power Sourcing Equipment) controls how to provision uninterruptible power through corresponding data ports (and cables) of the PSE to...
US-7,472,289 Audio noise mitigation for power state transitions
An audio noise mitigation approach. For one aspect, a first voltage associated with a first power management state is provided. A signal responsive to an...
US-7,472,288 Protection of processes running in a computer system
In one embodiment, a protected process is monitored by one or more watchdog processes. Upon detection that the protected process has been abnormally terminated,...
US-7,472,287 Method of protecting data saved to recording medium and disk drive adopting the method
An apparatus, a computer-readable recording medium, and a method of controlling data recording and reproducing to and from a disk. Controlling the recording of...
US-7,472,286 Selectively authorizing software functionality after installation of the software
Controlling access to functionality within an installed software product. The invention includes an authorization module that dynamically references...
US-7,472,285 Apparatus and method for memory encryption with reduced decryption latency
A method and apparatus for memory encryption with reduced decryption latency. In one embodiment, the method includes reading an encrypted data block from memory....
US-7,472,284 Method of, and system for detecting mass mailing viruses
A system for anti-virus processing an email having an executable attachment extracts structural elements of the email and examines the executable attachments for...
US-7,472,283 Method and apparatus for secured digital video and access tracking
The specification discloses a system and related method for tracking access to digital information that involves combining biometric information of a person...
US-7,472,282 Illegal access discriminating apparatus and method
ID information and organic information based on authentication demand which a service providing system received from a user terminal are inputted and stored into...
US-7,472,281 Method for the automatic log-in of a subscriber station situated particularly in a motor vehicle in an external...
In a method for the automatic log-in of a subscriber station in a motor vehicle into an external information system, a non-automatic log-in is first performed by...
US-7,472,280 Digital rights management
A method of managing digital rights comprises the following steps. First, a physical electronic key containing a first activation code is provided to a...
US-7,472,279 Method for automized and synchronous execution of customized code on off-loaded retrieved documents in a...
A technique for executing customized code on off-loaded or retrieved documents in a document processing environment. The present invention provides a code...
US-7,472,278 Remote authentication of an object using a signature encoded in a number of data portions
A method of authenticating an object in which a computer system receives indicating data from a sensing device. The indicating data is generated in response to...
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