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| Patent # | Description |
|---|---|
| US-7,472,277 |
User controlled anonymity when evaluating into a role A method, system, and program for user controlled anonymity when evaluating into a role are provided. An anonymous authentication controller enables a user to... |
| US-7,472,276 |
Data card verification system A method of verifying a pair of correspondents in electronic transaction, the correspondents each including first and second signature schemes and wherein the... |
| US-7,472,275 |
System and method of electronic signature verification A universal lightweight, easily carried memory identification card records information and controls access to this information. The memory card includes a file... |
| US-7,472,274 |
Authentication of an electronic tag A method and a system for authenticating an electronic tag by a host communicating with this tag via a reader, including: calculating, on the tag side, a first... |
| US-7,472,273 |
Authentication in data communication Method of authenticating a client comprising the steps of sending a subscriber identity to an authentication server; obtaining at least one challenge and at... |
| US-7,472,272 |
Digital asset usage accountability via event journaling A technique for establishing a perimeter of accountability for usage of digital assets such as data files. The accountability model not only tracks authorized... |
| US-7,472,271 |
Methods and devices relating to distributed computing environments The suitability of a service provider for performing a task having a sensitivity level is gauged by using a trust level associated with the provider, in... |
| US-7,472,270 |
Secure transmission of digital content between a host and a peripheral by
way of a digital rights management... A host securely transmits content to a peripheral thereof. The peripheral has a symmetric key (PK) and a copy of (PK) encrypted according to a public key (PU) of... |
| US-7,472,269 |
System and method for strong authentication achieved in a single round
trip A system and method for strong authentication achieved in a single round trip is disclosed, which reduces the amount of time needed for a mobile node to be... |
| US-7,472,268 |
Privacy and security mechanism for presence systems with tuple spaces A system is provided for cycling encryption keys to prevent the guessing of encrypted presence information in a shared information space. The system of the... |
| US-7,472,267 |
Convertible computer with selective activation of input devices based on a
tablet or notebook mode A convertible computer is equipped with a notebook computer function and a tablet computer function. When a system power supply is turned on, a functionality or... |
| US-7,472,266 |
Fault resilient boot in multi-processor systems In some embodiments a boot progress of a System Boot Strap Processor in a multi-processor system is monitored and a boot processor failure is detected using an... |
| US-7,472,265 |
Information input system, control method thereof, and storage medium This invention has as its object to provide an information input system which can flexibly select the storage location of information input from an input... |
| US-7,472,264 |
Predicting a jump target based on a program counter and state information
for a process One embodiment of the present invention provides a system that predicts a jump target for a jump instruction. During operation, the system starts fetching the... |
| US-7,472,263 |
Method and apparatus for prediction handling multiple branches
simultaneously A branch prediction apparatus includes a branch information receiving unit that receives simultaneously, branch information for each of a plurality of branch... |
| US-7,472,262 |
Methods and apparatus to prefetch memory objects by predicting program
states based on entropy values Methods and apparatus are disclosed to prefetch memory objects. An example method includes identifying program states associated with an executing program;... |
| US-7,472,261 |
Method for performing externally assisted calls in a heterogeneous
processing complex A method is provided for accessing, by an application running on a first processor, operating system services from an operating system running on a second... |
| US-7,472,260 |
Early retirement of store operation past exception reporting pipeline
stage in strongly ordered processor with... In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory... |
| US-7,472,259 |
Multi-cycle instructions In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI)... |
| US-7,472,258 |
Dynamically shared group completion table between multiple threads An SMT system has a dynamically shared GCT. Performance for the SMT is improved by configuring the GCT to allow an instruction group from each thread to complete... |
| US-7,472,257 |
Rerouting VLIW instructions to accommodate execution units deactivated
upon detection by dispatch units of... Processor (100) has a plurality of registers (120) for storing instructions for execution by the plurality of execution units (160). The plurality of registers... |
| US-7,472,256 |
Software value prediction using pendency records of predicted prefetch
values Profile information can be used to target read operations that cause a substantial portion of misses in a program. A software value prediction technique that... |
| US-7,472,255 |
Method for addressing a symbol in a memory and device for processing
symbols A bitwise addressing mode includes including the shaping of symbols of variable length during an operation for reading or writing a symbol in a bank of memories.... |
| US-7,472,254 |
Systems and methods for modifying a set of data objects A system and method for generating and updating a file system on a client computer. An original file system may be compared to an updated file system and the... |
| US-7,472,253 |
System and method for managing table lookaside buffer performance A computer system comprising a main memory and a processor die coupled to the main memory by a first bus. The processor die includes a processor core coupled to... |
| US-7,472,252 |
Merging identical memory pages Multiple virtual addresses map to the same physical location in memory if it has been determined that they are all intended to access the same data. In one... |
| US-7,472,251 |
Data storage apparatus detachably mounted to a host apparatus A data storage device including a non-volatile semiconductor memory and an attribute information storage unit. In an attribute information storage unit of the... |
| US-7,472,250 |
Storage control device, and control method for storage control device The storage control device of the present invention is able to perform input and output of data between blocks whose size is different with good efficiency. The... |
| US-7,472,249 |
Kernel memory free algorithm An approach for freeing memory based upon its relocatable or non-relocatable property is provided. In one embodiment, drivers and other processes that do not... |
| US-7,472,248 |
Techniques for generating serial presence detect contents Techniques are presented for automatically generating Serial Presence Detect (SPD) contents. Standards for specific values associated with SPD contents are... |
| US-7,472,247 |
Method and system for centralized memory management in wireless terminal
devices Methods and systems for controlling centralized memory management in wireless terminal devices. Memory management scripts associated with a wireless application... |
| US-7,472,246 |
Method and system for automated memory reallocating and optimization
between logical partitions A method and system for reallocating memory in a logically partitioned environment. The invention comprises a Performance Enhancement Program (PEP) and a... |
| US-7,472,245 |
System and method for securing drive access to data storage media based on
medium identifiers A method for securing access to a data medium comprises listing at least one unique identifier of media that a data transfer element is allowed to access in... |
| US-7,472,244 |
Scheme for securing a memory subsystem or stack A scheme for securing a memory subsystem or stack is disclosed. A first memory device performs an authentication on a received operation. If the authentication... |
| US-7,472,243 |
Storage system and control method thereof Upon receiving a primary/secondary switching command from a secondary host system, a secondary storage control device interrogates a primary storage control... |
| US-7,472,242 |
Eliminating duplicate blocks during backup writes Embodiments of the present invention include creating a subsequent backup copy of a data set by storing a full backup copy of the data set to reflect a state of... |
| US-7,472,241 |
Storage system and backup method A storage system and a backup method achieving enhanced reliability without degradation in the performance of the entire system. A first storage apparatus stores... |
| US-7,472,240 |
Storage system with plural control device affiliations The storage system includes a plurality of storage nodes and a control device coupling unit. Each of the storage nodes includes at least one storage device... |
| US-7,472,239 |
Storage system and data management method Provided are a storage system and data management method capable of improving the usage efficiency of a storage extent. With this storage system, a first storage... |
| US-7,472,238 |
Systems and methods for recovering electronic information from a storage
medium In one embodiment of the invention, a method is provided for retrieving certain electronic information previously stored on certain storage media after a... |
| US-7,472,237 |
Apparatus to offload and accelerate pico code processing running in a
storage processor Apparatus and method offloads processing from a networking processor operating in a storage environment. Three main functions are offloaded: semaphore... |
| US-7,472,236 |
Managing mirrored memory transactions and error recovery In a data processing system having a memory control device including at least two mirrored memory ports, a method and computer-readable medium for processing... |
| US-7,472,235 |
Multi-interfaced memory A multi-interfaced memory device includes an array of memory cells having a first interface and a second interface. The first interface and the second interface... |
| US-7,472,234 |
Method and system for reducing latency Embodiments generally relate to a method of reducing latency and cost. A device access request is received in a memory of non-local node over a NUMA interconnect... |
| US-7,472,233 |
Memory allocator for a multiprocessor computer system Methods for dynamically allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distributed shared... |
| US-7,472,232 |
Method and related apparatus for internal data accessing of computer
system Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory... |
| US-7,472,231 |
Storage area network data cache A cache connected to the virtualization engine in the center of a storage area network. The invention caches data in a virtual cache, without requiring... |
| US-7,472,230 |
Preemptive write back controller A preemptive write back controller is described. The present invention is well suited for a cache, main memory, or other temporarily private data storage that... |
| US-7,472,229 |
Bus controller initiated write-through mechanism A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the... |
| US-7,472,228 |
Read-copy update method A method for managing requests for deferred updates to shared data elements while minimizing grace period detection overhead associated with determining whether... |
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