Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,509,637 |
Method for automatically updating a computer registry A method for automatically registering resources required for an application program module to execute. After the application program module is booted, a... |
| US-7,509,636 |
System and method for updating files utilizing delta compression patching A system and method for updating one or more files on a computing device are provided. A client computing device obtains update information including an index... |
| US-7,509,635 |
Software and data file updating process A file updating process where a seed file is to be updated or revised to match a target file utilizes cached checking data to increase efficiency. Initially,... |
| US-7,509,634 |
SIMD instruction sequence generating program, SIMD instruction sequence
generating method and apparatus A translator receives a source code that is described using a process designation (such as a line-by-line process designation, a line data extraction... |
| US-7,509,633 |
System and method for grid-based distribution of Java project compilation A system for automatically segmenting the compilation of a large Java project under a controller node to a grid of slave nodes so as to reduce build time. A... |
| US-7,509,632 |
Method and apparatus for analyzing call history data derived from
execution of a computer program Call history data is sampled at fixed intervals during run-time, each sample representing only a limited portion of the stack. These data samples are... |
| US-7,509,631 |
Systems and methods for implementing a computer language type system The invention provides systems and methods for implementation of a computer language type system by augmenting finite state automata algorithms to accommodate... |
| US-7,509,630 |
Software component initialization in an ordered sequence A manager component of an apparatus in one example initializes a plurality of software components of a distributed software application, within one or more... |
| US-7,509,629 |
Method for system and architecture design using unified modeling language
(UML) To provide a UML design method by which architecture design pursuing optimal design parameters while viewing the overall target system on the UML model can be... |
| US-7,509,628 |
Extensibility framework for developing front office (CRM) workflow
automation components A method for enabling an existing business workflow tool to extend application functionality through the use of external components and for providing a business... |
| US-7,509,627 |
Method for management of dynamically alterable lifecycles in structured
classification domains A method for configuring multiple lifecycles, and associating each lifecycle with one or more subcategories of items includes receiving a request for a state... |
| US-7,509,626 |
Demonstrating proof of concept of a project with requirements component
providing weights on importance and... A system for demonstrating proof of concept of a project, such as a computer application, for an organization is provided. The system includes a requirements... |
| US-7,509,625 |
System and method for comprehensive code generation for system management A system and method for generating configuration code using an SNMP MIB, comprising generating a first configuration layer based on an XML MIB derived from the... |
| US-7,509,624 |
Method and apparatus for modifying a layout to improve manufacturing
robustness One embodiment of the present invention provides a system that modifies a layout to improve manufacturing robustness. During operation, the system receives a... |
| US-7,509,623 |
Manufacturing method of semiconductor device A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a... |
| US-7,509,622 |
Dummy filling technique for improved planarization of chip surface
topography The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based... |
| US-7,509,621 |
Method and apparatus for placing assist features by identifying locations
of constructive and destructive... One embodiment of the present invention provides a system that determines a location in a layout to place an assist feature. During operation, the system... |
| US-7,509,620 |
Dual phase shift photolithography masks for logic patterning A pair of phase shift photolithography masks and a process for deriving them is described. In one embodiment, the invention includes deriving a complex electric... |
| US-7,509,619 |
Auto generation of a multi-staged processing pipeline hardware
implementation for designs captured in high... A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model... |
| US-7,509,618 |
Method and apparatus for facilitating an adaptive electronic design
automation tool A method for designing systems on field programmable gate arrays (FPGAs) includes caching design information from a compilation of a system design. The design... |
| US-7,509,617 |
Design methodology to support relocatable bit streams for dynamic partial
reconfiguration of FPGAs to reduce... A method for generating a design for an FPGA provides for partial reconfiguration by allowing relocation of the same single bitstream within different areas of... |
| US-7,509,616 |
Integrated circuit layout design system, and method thereof, and program There is provided an integrated circuit layout design method capable of performing LVS verification in an early stage of layout design. Placement and routing... |
| US-7,509,615 |
Circuit layout structure and method A symmetrical circuit layout structure includes a number of signal wires, a ground wire and a dielectric layer. The signal wires include a first portion placed... |
| US-7,509,614 |
Method and system for integrating cores in FPGA-based system-on-chip (SoC) The invention provides an interface that can facilitate integration of user specific proprietary cores and commercially available cores during customization of... |
| US-7,509,613 |
Design method and architecture for power gate switch placement and
interconnection using tapless libraries A method and a structure provide a space efficient integrated circuit using standard cells and power gating by switch cells. The standard cells may be tapless,... |
| US-7,509,612 |
Method of designing semiconductor chip and program for use in designing
semiconductor chip Upon designing a standard cell type semiconductor chip, there are prepared a plurality of types of standard cells and a plurality of types of yield improvement... |
| US-7,509,611 |
Heuristic clustering of circuit elements in a circuit design An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired... |
| US-7,509,610 |
Timing analysis for programmable logic devices fabricated in different
Fabs Timing analysis of integrated circuits fabricated in different Fabs is described. A first speed file and a second speed file for a type of integrated circuit... |
| US-7,509,609 |
Methods and apparatus for reducing timing skew Reducing timing skew begins with identifying signals that are to have a reduced timing skew. These identified signals are then routed to reduce the layout... |
| US-7,509,608 |
Integrated system noise management--clock jitter A method for estimating jitter of an integrated circuit design is described. A description of logic blocks of the integrated circuit design is obtained. A... |
| US-7,509,607 |
Memory circuit having a crosstalk-glitch suppressor circuit and a control
device for controlling an amount of... The memory circuit comprises: a single or a plurality of reading-out port(s); a single or a plurality of writing port(s); a crosstalk-glitch suppressor circuit... |
| US-7,509,606 |
Method for optimizing power in a very large scale integration (VLSI)
design by detecting clock gating opportunities A computer implemented power optimization method that generates statistics relating to the clock gating of a set of components in a VLSI design. A set of... |
| US-7,509,605 |
Extending incremental verification of circuit design to encompass
verification restraints An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free... |
| US-7,509,604 |
Method and apparatus for formally comparing stream-based designs An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLM.sub.DFG and HLM.sub.DFG.... |
| US-7,509,603 |
Semiconductor integrated circuit and design method thereof A design method of a logic circuit, capable of shortening the design period, is achieved by this invention. A semiconductor integrated circuit has a plurality of... |
| US-7,509,602 |
Compact processor element for a scalable digital logic verification and
emulation system A logic simulation acceleration processor optimized for multi-value logic level simulation of electronic systems described in hardware description languages. |
| US-7,509,601 |
Design analysis workstation for analyzing integrated circuits A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital... |
| US-7,509,600 |
Generating test patterns having enhanced coverage of untargeted defects Disclosed below are representative embodiments of methods, apparatus, and systems for generating test patterns having an increased ability to detect untargeted... |
| US-7,509,599 |
Method and apparatus for performing formal verification using data-flow
graphs An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLM.sub.DFG and HLM.sub.DFG.... |
| US-7,509,598 |
Clock boosting systems and methods Systems and methods are disclosed herein to provide software clock boosting techniques. For example in one embodiment, a method of configuring a programmable... |
| US-7,509,597 |
Method and apparatus for performing post-placement functional
decomposition on field programmable gate arrays... A method for designing a system on a field programmable gate array (FPGA) includes using binary decision diagrams (BDDs) to perform functional decomposition on a... |
| US-7,509,596 |
Power distribution network simulation method using variable reduction
method A power distribution network simulation method capable of speedily and accurately analyzing a large power distribution network. In the power distribution network... |
| US-7,509,595 |
Method and system for enabling energy efficient wireless connectivity An apparatus and method that enables several different factors associated with the implementation of a particular wireless application to be considered in the... |
| US-7,509,594 |
Method of selling integrated circuit dies for multi-chip packages An integrated circuit has a plurality of bonding pads, at least one of which is adapted to be directly electrically connected to a bonding pad of another... |
| US-7,509,593 |
Mouse sound volume control A distance between a cursor and an object displayed on a Web page or other image automatically controls a volume with which an audio file associated with the... |
| US-7,509,592 |
Spotlight cursor An apparatus and method is disclosed for displaying a secondary layer of information in a graphical user interface where the second layer of information is... |
| US-7,509,591 |
Generation engine for a treemap display A treemap generation engine enables a user of a treemap generation application to design a treemap display page by providing inputs that define the format of the... |
| US-7,509,590 |
Representing three-dimensional data A machine-readable definition of a scene including three dimensional objects is represented. A schematic representation of the scene displays an object in which... |
| US-7,509,589 |
Storage domain GUI A method generates a graphical portion of a graphical user interface (GUI), the graphical portion concerning aspects of a storage domain. Such a method may... |
| US-7,509,588 |
Portable electronic device with interface reconfiguration mode A portable electronic device displays a plurality of icons (e.g., graphical objects) in a region in a touch-sensitive display; detects a predefined user action,... |
Copyright 2008−2012 Patents.com
