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| Patent # | Description |
|---|---|
| US-7,508,731 |
Semiconductor memory device with a fixed burst length having column
control unit The present invention relates to a semiconductor memory device with a fixed burst length, including a column control circuit, the semiconductor memory device... |
| US-7,508,730 |
Semiconductor memory devices having control circuitry to avoid recovering
a charge pump when executing... A semiconductor device includes a memory cell array and a command interface that is configured to receive a command from outside of the semiconductor memory... |
| US-7,508,729 |
Oscillator circuit generating oscillating signal having stable cycle An oscillator circuit includes a capacitor, a first constant current source electrically couplable to an end of the capacitor, a second constant current source... |
| US-7,508,728 |
Methods and apparatus to provide refresh for global out of range read
requests Methods and apparatus to provide refresh when an out of range address is received are disclosed. An example method of providing a refresh signal to a memory cell... |
| US-7,508,727 |
Memory structure and data writing method thereof A memory structure and data writing method thereof includes a power supply circuit and a bridge circuit. The bridge circuit is driven by the power supply... |
| US-7,508,726 |
Signal sensing circuit and semiconductor memory device using the same A signal sensing circuit and a semiconductor memory device using the same are provided. The signal sensing circuit comprises a sense amplifier, a kick... |
| US-7,508,725 |
Semiconductor memory device A semiconductor memory device is disclosed, which includes a memory cell array including a plurality of memory cells, a built-in self-test circuit which writes... |
| US-7,508,724 |
Circuit and method for testing multi-device systems A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial... |
| US-7,508,723 |
Buffered memory device A memory module having a DRAM device configured to generate a low DQS state on a DQS line, and a buffer coupled to the DRAM device, the buffer having a plurality... |
| US-7,508,722 |
Memory device having strobe terminals with multiple functions A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device... |
| US-7,508,721 |
Use of data latches in multi-phase programming of non-volatile memories A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick... |
| US-7,508,720 |
Systems for comprehensive erase verification in non-volatile memory Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor... |
| US-7,508,719 |
Non-volatile memory cell circuit with programming through band-to-band
tunneling and impact ionization gate current Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor... |
| US-7,508,718 |
Method for operating a non-volatile charge-trapping memory device and
method for determining programming/erase... A method for determining programming/erase conditions and a method for operating a charge-trapping semiconductor device are disclosed. Programming and erase... |
| US-7,508,717 |
Reading circuit for semiconductor memory A reading circuit for reading semiconductor memory cells, adapted to be coupled to at least one memory cell and to at least one reference cell through a... |
| US-7,508,716 |
Sense amplifier for low-supply-voltage nonvolatile memory cells A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a... |
| US-7,508,715 |
Coarse/fine program verification in non-volatile memory using different
reference levels for improved sensing Coarse/fine programming of non-volatile memory is provided in which memory cells are programmed at a first rate of programming prior to reaching a coarse verify... |
| US-7,508,714 |
Memory array incorporating mirrored NAND strings and non-shared global bit
lines within a block An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices... |
| US-7,508,713 |
Method of compensating variations along a word line in a non-volatile
memory Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line... |
| US-7,508,712 |
Nonvolatile semiconductor memory device and control method thereof A nonvolatile semiconductor memory device includes a memory cell array 101 having a plurality memory strings, each of said plurality of memory strings having a... |
| US-7,508,711 |
Arrangements for operating a memory circuit In one embodiment a method for programming memory cells is disclosed. The method can include applying a programming voltage to a selected memory cell during a... |
| US-7,508,710 |
Operating non-volatile memory with boost structures A method for operating non-volatile memory having boost structures. The boost structures are provided for individual NAND strings and can be individually... |
| US-7,508,709 |
Page buffer circuit with reduced size and methods for reading and
programming data with the same A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a... |
| US-7,508,708 |
NAND string with a redundant memory cell The invention provides methods and apparatus. A NAND memory block has a source select line for selectively coupling one or more strings of series-coupled... |
| US-7,508,707 |
Semiconductor storage apparatus Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip.... |
| US-7,508,706 |
Nonvolatile semiconductor memory device provided with data register for
temporarily holding data in memory array A precharge signal generation circuit outputs a precharge signal including a pulse every access cycle with respect to a data register in a first mode, and... |
| US-7,508,705 |
Method for programming a multi-level non-volatile memory device A method for programming multi-level non-volatile memory including at least one flag cell and a plurality of multi-bit storage cells. Each storage cell stores... |
| US-7,508,704 |
Non-volatile semiconductor storage system In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control... |
| US-7,508,703 |
Non-volatile memory with boost structures A non-volatile memory having boost structures. Boost structures are provided for individual NAND strings and can be individually controlled to assist in... |
| US-7,508,702 |
Programming method of magnetic random access memory A programming method of a magnetic random access memory (MRAM) is provided. The magnetic random access memory includes a first magnetic pinned layer, a second... |
| US-7,508,701 |
Negative differential resistance devices and approaches therefor Negative differential resistance devices are implemented to facilitate current flow under different operating conditions. According to an example embodiment of... |
| US-7,508,700 |
Method of magnetic tunneling junction pattern layout for magnetic random
access memory An MTJ pattern layout for a memory device is disclosed that includes two CMP assist features outside active MTJ device blocks. A first plurality of dummy MTJ... |
| US-7,508,699 |
Magnetic memory device and method An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first... |
| US-7,508,698 |
Memory array with a delayed wordline boost Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets... |
| US-7,508,697 |
Self-repairing technique in nano-scale SRAM to reduce parametric failures A self-repairing SRAM and a method for reducing parametric failures in SRAM. On-chip leakage or delay monitors are employed to detect inter-die Vt process... |
| US-7,508,696 |
Decoupling capacitor for semiconductor integrated circuit device A decoupling capacitor includes a first MOS transistor having a first conductivity type. The first MOS transistor functions as a resistor element due to an... |
| US-7,508,695 |
Nonvolatile semiconductor memory device and data writing method A data writing method for writing data sequentially in a cross-point memory cell array having a variable resistive element whose electric resistance is changed... |
| US-7,508,694 |
One-time-programmable memory A one-time-programmable memory cell uses two complementary antifuses that are programmed in a complementary fashion such that only one of the two complementary... |
| US-7,508,693 |
One-time-programmable (OTP) memory device and method for testing the same An OTP memory device and method for testing the same is disclosed. The memory device includes a number of memory cells and each memory cell has an initial... |
| US-7,508,692 |
Semiconductor memory device and semiconductor device group A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and... |
| US-7,508,691 |
Memory arrangement with low power consumption A memory arrangement, particularly a ROM, having memory cells, local virtual supply voltage lines, word lines and result lines may also include global virtual... |
| US-7,508,690 |
Monitoring and control device and bridge module therefor Disclosed is a monitoring and/or control device (1) having an assembly of system modules (S.sub.i) in the form of field bus coupler modules, supply modules... |
| US-7,508,689 |
Inverter and a drive system using the inverter A inverter has a switching device for switching DC to change it to AC, and a bipolar type rechargeable battery connected to the switching device in parallel or... |
| US-7,508,688 |
Method and arrangement for measuring output phase currents of a voltage
source inverter under a load A method and arrangement for measuring output phase currents of a voltage source inverter when the inverter is connected to a load, the method comprising, during... |
| US-7,508,687 |
Power supply that reads power requirement information across a DC power
cord from a load A power supply device that is capable of outputting multiple different output voltages is coupled by a DC power supply cord to an electrical device. An unpowered... |
| US-7,508,686 |
System and method for configuring direct current converter A method and system to determine a battery mode of an integrated circuit device are presented. The battery mode is selected with respect to first and second... |
| US-7,508,685 |
Stabilized power supply A stabilized power supply for X-ray tubes having a first rectifier circuit, an inverter circuit comprising main switches, a transformer, a second rectifier... |
| US-7,508,684 |
Handheld electronic device including multi-compartment shielding container
and associated methods A handheld electronic device may include a portable housing and a shielding container within the portable housing. The shielding container may include a... |
| US-7,508,683 |
Input/output module computer server door Methods and apparatus for providing electromagnetic interference (EMI) shielding for a module receiving area within a computer server housing configured to... |
| US-7,508,682 |
Housing for an electronic circuit A housing for an electrical circuit having a metal base with an open top and a metal lid which overlies the open top of the base and forms an interior chamber... |
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