Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,507,679 |
Paper machine fabric A paper machine fabric comprising at least two machine direction yarn systems, which are bound together by means of a binding yarn system. The layer of the... |
| US-7,507,678 |
Method and apparatus for forming oxynitride film and nitride film,
oxynitride film, nitride film, and substrate Uniform oxynitride and nitride films can be formed by low-temperature and high-speed nitriding reaction not dependent on the nitriding time or nitriding... |
| US-7,507,677 |
Removable amorphous carbon CMP stop A method is provided for processing a substrate including removing amorphous carbon material disposed on a low k dielectric material with minimal or reduced... |
| US-7,507,676 |
Film formation method and apparatus for semiconductor process An insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas,... |
| US-7,507,675 |
Device manufacturing method and device A method for patterning a polished silicon surface is disclosed, the method including steps leading to an organic monolayer on at least a part of the silicon... |
| US-7,507,674 |
Memory device including resistance change layer as storage node and
method(s) for making the same A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and... |
| US-7,507,673 |
Method for etching an object to be processed An object to be process has a structure having an SiC film 61 and an organic Si-low dielectric constant film 62 formed on the SiC film 61. The SiC film 61 is... |
| US-7,507,672 |
Plasma etching system and method A system and a process for plasma etching a semiconductor device. The technique comprises periodically applying a heightened voltage bias during the plasma... |
| US-7,507,670 |
Silicon electrode assembly surface decontamination by acidic solution Methods for cleaning silicon surfaces of electrode assemblies by efficiently removing contaminants from the silicon surfaces without discoloring the silicon... |
| US-7,507,669 |
Gap tuning for surface micromachined structures in an epitaxial reactor A device includes a top layer having at least two opposing faces, and at least two epitaxially deposited layers, each of the at least two epitaxially deposited... |
| US-7,507,668 |
Polishing slurry, method of treating surface of
Ga.sub.xIn.sub.1-xAs.sub.yP.sub.1-y crystal and
... The present polishing slurry is a polishing slurry for chemically mechanically polishing a surface of a Ga.sub.xIn.sub.1-xAs.sub.yP.sub.1-y crystal... |
| US-7,507,667 |
Selective heating using flash anneal A copper film is treated by applying light at short wavelengths, e.g., at less than 0.6 .mu.m, to heat the copper film and generate a large temperature gradient... |
| US-7,507,666 |
Manufacture method for semiconductor device having concave portions filled
with conductor containing Cu as its... An insulating film having a concave portion is formed on a semiconductor substrate. The inner surface of the concave portion and the upper surface of the... |
| US-7,507,665 |
Method of manufacturing electrical parts A method of manufacturing electrical parts is provided, which method comprises the steps of: forming a photoresist on a part of the surface of a substrate;... |
| US-7,507,664 |
Tungsten plug corrosion prevention method using ionized air Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming... |
| US-7,507,663 |
Fabrication of semiconductor devices Fabrication of microelectronic devices is accomplished using a substrate having a recessed pattern. In one approach, a master form is used to replicate a... |
| US-7,507,662 |
Ferroelectric memory and its manufacturing method A ferroelectric memory includes a substrate, an interlayer dielectric layer composed of at least one layer formed above the substrate, a plurality of... |
| US-7,507,661 |
Method of forming narrowly spaced flash memory contact openings and
lithography masks A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device... |
| US-7,507,660 |
Deposition processes for tungsten-containing barrier layers In one embodiment, a method for forming a barrier material on a substrate is provided which includes exposing a dielectric layer on the substrate to a plasma... |
| US-7,507,659 |
Fabrication process of a semiconductor device A method for fabricating a semiconductor device has forming an opening defined by an inner wall surface in an insulation film, covering said inner wall surface... |
| US-7,507,658 |
Semiconductor apparatus and method of fabricating the apparatus A via hole is formed by a first step of forming an opening in a resin insulating film by laser radiation, a second step of forming an opening in said resin... |
| US-7,507,657 |
Method for fabricating storage node contact in semiconductor device Disclosed is a method for fabricating a plurality of storage node contacts in a semiconductor device capable of minimizing an influence of a slurry residue and... |
| US-7,507,656 |
Method and structure for low k interlayer dielectric layer An integrated circuit interconnect structure. The structure includes a substrate and a layer of transistor elements overlying the substrate. A first interlayer... |
| US-7,507,655 |
Method of forming solder connection portions, method of forming wiring
substrate and method of producing... A method of forming solder connection portions on first electrode pads and on second electrode pads, comprises a first step of arranging solder balls on the... |
| US-7,507,654 |
Method for mounting electronic element on a circuit board Method for mounting an electronic component on a circuit board firstly flip-chip bonding positioning bumps of the electronic component to pads of the circuit... |
| US-7,507,653 |
Method of fabricating metal compound dots dielectric piece A method of fabricating a dielectric piece which includes metal compound dots is provided. A stacked layer formed over the substrate includes a metal compound... |
| US-7,507,652 |
Methods of forming a composite dielectric structure and methods of
manufacturing a semiconductor device... Some methods that are provided form a composite dielectric structure on a substrate. A first dielectric layer that includes metal and oxygen is formed on a... |
| US-7,507,651 |
Method for fabricating semiconductor device with bulb shaped recess gate
pattern A method for fabricating a semiconductor device with a bulb shaped recess gate pattern includes selectively etching a first portion of a substrate to form a... |
| US-7,507,650 |
Process for producing Schottky junction type semiconductor device A process for producing a Schottky junction type semiconductor device includes the steps of forming a Schottky electrode on a surface of a silicon carbide... |
| US-7,507,649 |
Method for electrical doping a semiconductor material with Cesium The invention relates to a method for doping a semiconductor material with Cesium, wherein said semiconductor material is exposed to a cesium vapor. Said Cesium... |
| US-7,507,648 |
Methods of fabricating crystalline silicon film and thin film transistors A method by which solid phase crystallization (SPC) thermal budget for crystallizing an undoped (or a lightly doped) amorphous Si (a-Si) is significantly... |
| US-7,507,647 |
Method of manufacturing a high voltage semiconductor device including a
deep well and a gate oxide layer... A method of manufacturing a high voltage semiconductor device including forming a P-type region implanted with P-type impurities and an N-type region implanted... |
| US-7,507,646 |
Semiconductor devices and method of manufacturing them With conventional device, the quantity of complex defects differs with each semiconductor device because the concentration of impurities intrinsically contained... |
| US-7,507,645 |
Method of forming polycrystalline semiconductor layer and thin film
transistor using the same A method of forming a polycrystalline semiconductor layer includes forming a semiconductor layer of amorphous silicon on a substrate, forming a plurality of spot... |
| US-7,507,644 |
Method of forming dielectric layer of flash memory device A method of manufacturing a flash memory device, wherein according to one embodiment, when a high dielectric material is formed by a remote plasma atomic layer... |
| US-7,507,643 |
Method for manufacturing semiconductor substrate, method for manufacturing
semiconductor device, and... A method for manufacturing a semiconductor substrate includes forming a first semiconductor layer on a semiconductor base; forming a second semiconductor layer... |
| US-7,507,642 |
Vapor-phase growth method, semiconductor manufacturing method and
semiconductor device manufacturing method In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method... |
| US-7,507,641 |
Method of producing bonded wafer A bonded wafer is produced by implanting ions of a light element into a wafer for active layer to a predetermined depth position to form an ion implanted layer,... |
| US-7,507,640 |
Method for producing silicon wafer A method for producing a silicon wafer, comprising performing an activation of metallic impurities by irradiating laser light on the metallic impurities... |
| US-7,507,639 |
Wafer dividing method A method of dividing a wafer having devices formed in a plurality of areas sectioned by a plurality of dividing lines, into individual chips along the dividing... |
| US-7,507,638 |
Ultra-thin die and method of fabricating same In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on... |
| US-7,507,637 |
Method of manufacturing wafer level stack package To manufacture a wafer level stack package, first and second wafers having first and second via patterns are prepared. The second wafer is attached to the first... |
| US-7,507,636 |
Amorphous Si/Au eutectic wafer bonding structure An amorphous Si (silicon)/Au (gold) eutectic wafer bonding structure is fabricated. An amorphous Si obtained through coating or growth contacts with Au for... |
| US-7,507,635 |
CMOS image sensor and method of fabricating the same A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and... |
| US-7,507,634 |
Method for fabricating a localize SOI in bulk silicon substrate including
changing first trenches formed in the... To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying... |
| US-7,507,633 |
Method and structure for improved alignment in MRAM integration A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the... |
| US-7,507,632 |
Semiconductor device and manufacturing method thereof In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film... |
| US-7,507,631 |
Epitaxial filled deep trench structures A method of forming and a structure of an electronic device. The method including: forming a trench in a single-crystal semiconductor substrate; forming a dopant... |
| US-7,507,630 |
Method of fabricating a semiconductor device A method of fabricating a semiconductor device includes: forming an insulating film on a semiconductor body to cover a termination area surrounding a cell area;... |
| US-7,507,629 |
Semiconductor devices having an interfacial dielectric layer and related
methods A semiconductor device includes a semiconductor substrate including silicon and an oxide layer on the substrate. The oxide layer includes silicon. An interfacial... |
Copyright 2008−2012 Patents.com
