Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,509,487 |
Secure networking using a resource-constrained device Secure communication between a resource-constrained device and remote network nodes over a network with the resource-constrained acting as a network node. The... |
| US-7,509,486 |
Encryption processor for performing accelerated computations to establish
secure network sessions connections Methods and apparatus for an encryption processor for performing accelerated computations to establish secure network sessions. The encryption processor includes... |
| US-7,509,485 |
Method for loading a program module in an operating system A method for loading a program module in an operating system is provided. An application program is launched and at least one main program module thereof is... |
| US-7,509,484 |
Handling cache misses by selectively flushing the pipeline An apparatus and method for efficiently managing data cache load misses is described in connection with a multithreaded, pipelined multiprocessor chip. A CMT... |
| US-7,509,483 |
Methods and apparatus for meta-architecture defined programmable
instruction fetch functions supporting... A computing architecture and software techniques are described which modifies the basic sequential instruction fetching mechanism of a processor by separating a... |
| US-7,509,482 |
Orderly processing ready entries from non-sequentially stored entries
using arrival order matrix reordered upon... A memory device stores entries waiting to be processed. Row numbers of matrix information correspond to storage positions within the memory device, column... |
| US-7,509,481 |
Patchable and/or programmable pre-decode Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered... |
| US-7,509,480 |
Selection of ISA decoding mode for plural instruction sets based upon
instruction address An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different... |
| US-7,509,479 |
Reconfigurable global cellular automaton with RAM blocks coupled to input
and output feedback crossbar switches... The invention relates to a computer containing a RAM-based primary part (Ht) with a stucturable RAM unit (2). On the input side, a first crossbar switch (1) is... |
| US-7,509,478 |
Program memory space expansion for particular processor instructions A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses... |
| US-7,509,477 |
Aggregating data from difference sources A method and system that aggregates data associated with one or more entities from different data sources are provided. The data sources include documents, web... |
| US-7,509,476 |
Advanced processor translation lookaside buffer management in a
multithreaded system Advanced processors for executing software applications on different operating system are presented including: a number of processor cores each configured to... |
| US-7,509,475 |
Virtual machine control method and virtual machine system having host page
table address register A virtual machine control method and a virtual machine system are disclosed. In the case where a guest program can be operated in a plurality of address... |
| US-7,509,474 |
Robust index storage for non-volatile memory A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile... |
| US-7,509,473 |
Segmented storage system mapping A system for mapping between logical addresses and storage units of a plurality of storage volumes which comprise a storage system. For each volume, logical... |
| US-7,509,472 |
Collapsible front-end translation for instruction fetch Address translation for instruction fetching can be obviated for sequences of instruction instances that reside on a same page. Obviating address translation... |
| US-7,509,471 |
Methods for adaptively handling data writes in non-volatile memories A memory system is presented where sectors are normally stored in logically contiguous groups. As repeated writes of the same small sector group can causes a... |
| US-7,509,470 |
System and method for dynamic sizing of cache sequential list A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space... |
| US-7,509,469 |
Semiconductor memory asynchronous pipeline An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data... |
| US-7,509,468 |
Policy-based data protection A method, system, computer system, and computer-readable medium to trigger protection of a set of data based upon the type or class of the data in the set and/or... |
| US-7,509,467 |
Storage controller and data management method Upon receiving a primary/secondary switching command from a secondary host system, a secondary storage control device interrogates a primary storage control... |
| US-7,509,466 |
Backup method for a copy pair using newly created logical volume via
virtual server device Provided is a technology in which: a request-source storage device provides a request-source server device with a storage area of a disk drive as at least one... |
| US-7,509,465 |
System and method for managing memory or session resources used for
movement of data being copied in a data... This invention is a system and method for managing and allocating memory used for data movement of data being copied in a data storage environment. In one... |
| US-7,509,464 |
System and method for identifying empty locations in a scrambled memory A system includes a memory operable to store scrambled data at a plurality of memory locations. The system also includes an empty detector operable to determine... |
| US-7,509,463 |
Cell processor atomic compare and swap using dedicated synergistic
processor element An atomic compare and swap operation that can be implemented in processor system having a power processor element (PPE) and a synergistic processor element (SPE)... |
| US-7,509,462 |
Advanced processor with use of bridges on a data movement ring for optimal
redirection of memory and I/O traffic An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is... |
| US-7,509,461 |
Method and apparatus for intelligent buffer cache pre-emption The present invention augments each entry in a memory frame table to include information associated with the availability of any page that is buffer cache... |
| US-7,509,460 |
DRAM remote access cache in local memory in a distributed shared memory
system In one embodiment, a memory controller for a node in a multi-node computer system comprises logic and a control unit. The logic is configured to determine if an... |
| US-7,509,459 |
Microprocessor with improved data stream prefetching A microprocessor has a plurality of stream prefetch engines for prefetching a respective data stream from the system memory into the microprocessor cache memory... |
| US-7,509,457 |
Non-homogeneous multi-processor system with shared memory A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular... |
| US-7,509,456 |
Apparatus and method for discovering a scratch pad memory configuration The invention includes a method of debugging an embedded processor. Scratch pad memory of an embedded processor is accessed to form a configuration file... |
| US-7,509,455 |
Information processing system having volume guard function In a system comprising a first storage system providing plural first logical volumes including real logical volume and a virtual logical volume with a host, a... |
| US-7,509,454 |
System and method for managing disk space in a thin-provisioned storage
subsystem A system and method for managing disk space in a thin-provisioned storage subsystem. If a number of free segments in a free segment pool at a storage subsystem... |
| US-7,509,453 |
Pseudo-mounting unformatted removable media An invention is disclosed for automatically formatting removable media. A default media image is generated in computer memory in response to detecting... |
| US-7,509,452 |
Image forming apparatus, erasing method, and hard disk management method An image forming apparatus includes a plurality of erase information each showing whether or not to erase data for each of a plurality of divided areas into... |
| US-7,509,451 |
Method and circuit for updating a software register in semiconductor
memory device A method and circuit for updating a software register is disclosed, wherein the software register is updated using data received through a data I/O pad, and the... |
| US-7,509,450 |
Microcontrol architecture for a system on a chip (SoC) A data processing system includes a main processor that runs an operating system; a microcontrol processor coupled to the main processor that controls a first... |
| US-7,509,449 |
Internet SCSI communication via UNDI services A method and system for emulating a hardware Internet Small Computer System Interface (iSCSI) Host Bus Adapter (HBA) without risking an interruption of... |
| US-7,509,448 |
Systems and methods for managing semantic locks In one embodiment, a system for managing semantic locks and semantic lock requests for a resource is provided. Access to the resource is controlled such that... |
| US-7,509,447 |
Barrel-incrementer-based round-robin apparatus and instruction dispatch
scheduler employing same for use in... An apparatus for selecting one of N requestors of a shared resource in a round-robin fashion is disclosed. One or more of the N requestors may be disabled from... |
| US-7,509,446 |
IIC bus communication system capable of suppressing freeze of IIC bus
communication due to a noise and method... Multiple master devices and multiple slave devices are connected in parallel to two bus lines including a SCL line 1 and a SDA line 2, and a pullup resistor is... |
| US-7,509,445 |
Adapting a plurality of measurement cartridges using cartridge controllers System and method for controlling cartridges to perform industrial operation(s). The system may include cartridge controllers coupled to the cartridges, timing... |
| US-7,509,444 |
Data access device for working with a computer of power off status This invention discloses a data access device for using in computer of power off status, which comprises a power multiplexer, a DC to DC converter, a serial bus... |
| US-7,509,443 |
Storage management system and method using performance values to obtain
optimal input/output paths within a... A CPU of a performance management server, upon receipt of a request from a keyboard or a mouse to newly assign an application to a specified application server,... |
| US-7,509,442 |
Informational-signal-processing apparatus, functional block, and method of
controlling the functional block An informational-signal-processing apparatus has a plurality of functional blocks and a control block that controls operations of the functional blocks. Each of... |
| US-7,509,441 |
Systems and methods for segmenting and protecting a storage subsystem A storage subsystem comprises a set of zone definitions that uses physical block addresses to divide a memory array in the storage subsystem into zones or... |
| US-7,509,440 |
Programmable controller and communication unit therefor A programmable controller includes a CPU unit, a communication unit and peripheral units connected together through an internal bus. The communication unit has a... |
| US-7,509,439 |
Method for maintaining register integrity and receive packet protection
during ULPI PHY to LINK bus transactions A system and method for protecting register write operations, especially register write operations performed in a USB PHY. A USB transmitter/receiver, operable... |
| US-7,509,438 |
Bi-directional line switched ring support for path trace monitoring on a
protection path Methods and apparatus for enabling a protection path within a network to be monitored are disclosed. According to one aspect of the present invention, a method... |
| US-7,509,437 |
Federated multiprotocol communication Methods, apparatus, and business techniques are disclosed for use in distributed communication systems comprising a plurality of communication protocols. In one... |
Copyright 2008−2012 Patents.com
