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| Patent # | Description |
|---|---|
| US-7,512,037 |
Method and apparatus for acoustic system having a transceiver module An acoustic method and apparatus for an acoustic system use a transceiver module, which can transmit to a transmit acoustic element of a transmit sonar array and... |
| US-7,512,036 |
Underwater acoustic positioning system and method A method for determining the position of an underwater device includes placement of a plurality of station keeping devices on or below the surface of the water... |
| US-7,512,035 |
Piezoelectric actuator, liquid transporting apparatus, and method of
producing piezoelectric actuator A piezoelectric actuator includes a vibration plate covering pressure chambers and serving also as a common electrode, a piezoelectric layer arranged entirely on... |
| US-7,512,034 |
Drill noise seismic data acquisition and processing methods A method of acquiring seismic data that includes deploying a first array of seismic receivers and a second array of seismic receivers, and simultaneously... |
| US-7,512,033 |
Apparatus and method for controlling clock signal in semiconductor memory
device An operation clock controller for preventing a semiconductor memory device from operating when an operation frequency of an external clock is higher than a... |
| US-7,512,032 |
Electronic device comprising non volatile memory cells with optimized
programming and corresponding programming... A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with... |
| US-7,512,031 |
Semiconductor device including voltage level conversion output circuit A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first... |
| US-7,512,030 |
Memory with low power mode for WRITE The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to... |
| US-7,512,029 |
Method and apparatus for managing behavior of memory devices A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it... |
| US-7,512,028 |
Integrated circuit feature definition using one-time-programmable (OTP)
memory In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature... |
| US-7,512,027 |
Refresh control circuit in semiconductor memory apparatus and method of
controlling period of refresh signal... A refresh control circuit includes a temperature detecting unit that detects the temperature and generates a temperature detecting voltage, a control unit that... |
| US-7,512,026 |
Sense amplifying circuit capable of operating with lower voltage and
nonvolatile memory device including the same A sense amplifying circuit capable of operating with a lower voltage and/or a nonvolatile memory device including the same may be provided. The nonvolatile... |
| US-7,512,025 |
Open digit line array architecture for a memory array A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and... |
| US-7,512,024 |
High-speed memory device easily testable by low-speed automatic test
equipment and input/output pin control... The present invention provides a high-speed memory device that can be easily tested using the existing low-speed Automatic Test Equipment (ATE). In an embodiment... |
| US-7,512,023 |
Memory and method for improving the reliability of a memory having a used
memory region and an unused memory region A method for improving the reliability of a memory having a used memory region and an unused memory region, wherein defect memory elements in the used memory... |
| US-7,512,022 |
Non-volatile memory structure A non-volatile memory array structure includes N bit lines, M first word lines, M.times.N first memory cells, a second word line, n repair circuits and a sense... |
| US-7,512,021 |
Register configuration control device, register configuration control
method, and program for implementing the... A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit... |
| US-7,512,020 |
Nonvolatile memory device with load-free wired-OR structure and an
associated driving method A nonvolatile semiconductor memory device includes an internal output line, and a page buffers. Each page buffer is coupled to at least one bitline, the internal... |
| US-7,512,019 |
High speed digital signal input buffer and method using pulsed positive
feedback An input buffer generates an output signal corresponding to a digital input signal. The input buffer is coupled to a feedback circuit. The feedback circuit... |
| US-7,512,018 |
Column address enable signal generation circuit for semiconductor memory
device A semiconductor memory device includes a clock period detector, a column address enable signal generator, and a multiplexing circuit. The clock period detector... |
| US-7,512,017 |
Integration of planar and tri-gate devices on the same substrate An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain;... |
| US-7,512,016 |
Method of programming and erasing a p-channel be-SONOS NAND flash memory A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results... |
| US-7,512,015 |
Negative voltage blocking for embedded memories In one embodiment, a memory is provided that includes: a memory cell array adapted to be programmed with a positive voltage from a positive-negative node and to... |
| US-7,512,014 |
Comprehensive erase verification for non-volatile memory Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor... |
| US-7,512,013 |
Memory structures for expanding a second bit operation window A charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing in a left charge storage site and a right charge... |
| US-7,512,012 |
Non-volatile memory and manufacturing method and operating method thereof
and circuit system including the... The memory cell includes a first unit, a semiconductor layer, a second unit, and a doped region. The first unit includes a first gate, a first charge trapping... |
| US-7,512,011 |
Method of reading data in a non-volatile memory device A method of reading data in a non-volatile memory device includes providing a plurality of blocks and a plurality of bit lines, each block having a plurality of... |
| US-7,512,010 |
Voltage regulator for flash memory device Provided is a voltage regulator of a flash memory device. Embodiments of the invention provide a voltage regulator that is configured to regulate either an... |
| US-7,512,009 |
Method for programming a reference cell A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative... |
| US-7,512,008 |
Circuit to control voltage ramp rate A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory... |
| US-7,512,007 |
Data processing device A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can... |
| US-7,512,006 |
Non-volatile memory and semiconductor device There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a... |
| US-7,512,005 |
NAND memory with side-tunneling A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel... |
| US-7,512,004 |
Semiconductor memory device having stacked gate including charge
accumulation layer and control gate and test... A semiconductor memory device includes a memory cell, a word line, a bit line, a column gate, and a power supply decode circuit. The memory cell has a first MOS... |
| US-7,512,003 |
Non-volatile memory device A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the... |
| US-7,512,002 |
Non-volatile memory device and programming, reading and erasing methods
thereof A non-volatile memory device includes a memory cell array and a voltage control unit. The memory cell array includes a plurality of memory blocks each including... |
| US-7,512,001 |
Semiconductor memory device, test system including the same and repair
method of semiconductor memory device A semiconductor memory device includes an array having memory cells arranged in rows and columns; a clock-to-address converter for counting an external clock... |
| US-7,512,000 |
Memory unit A memory unit is provided herein. The present invention utilizes two non-volatile devices having a split gate structure to save a logic state of the memory unit.... |
| US-7,511,999 |
MIS-transistor-based nonvolatile memory with reliable data retention
capability A nonvolatile semiconductor memory device includes a nonvolatile memory cell including an odd number of MIS transistor pairs, each of which stores one-bit data... |
| US-7,511,998 |
Non-volatile memory device and method of fabricating the same A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a... |
| US-7,511,997 |
Semiconductor memory device A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell being settable to have one of plural physical... |
| US-7,511,996 |
Flash memory program inhibit scheme A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased... |
| US-7,511,995 |
Self-boosting system with suppression of high lateral electric fields In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a... |
| US-7,511,994 |
MEM suspended gate non-volatile memory A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing... |
| US-7,511,993 |
Phase change memory device and related programming method A phase change memory device comprises a memory cell array and a write driver circuit. The memory cell array comprises a plurality of memory cells, and the write... |
| US-7,511,992 |
Magnetic memory device There is provided a magnetic memory device including a first magnetoresistive element which takes a high-resistance-state when receiving a write current in a... |
| US-7,511,991 |
Spin-injection magnetic random access memory A spin-injection magnetic random access memory according to an embodiment of the invention includes a magnetoresistive element having a magnetic fixed layer... |
| US-7,511,990 |
Magnetic tunnel junction temperature sensors An integrated circuit device is provided which includes a heat source disposed in a substrate, and a Magnetic Tunnel Junction ("MTJ") temperature sensor disposed... |
| US-7,511,989 |
Memory cells in double-gate CMOS technology provided with transistors with
two independent gates This invention relates to an improved microelectronic RAM memory device, provided with 4T or 6T cells made using the double gate technology and each associated... |
| US-7,511,988 |
Static noise-immune SRAM cells A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and... |
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