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| Patent # | Description |
|---|---|
| US-7,510,982 |
Creation of porosity in low-k films by photo-disassociation of imbedded
nanoparticles Porous dielectric layers are produced by embedding and removing nanoparticles in composite dielectric layers. The pores may be produced after the barrier... |
| US-7,510,981 |
Method for manufacturing semiconductor device A semiconductor device includes an element isolation film, which exhibits less variations in the height dimension from the surface of the substrate and has a... |
| US-7,510,980 |
Method for manufacturing semiconductor device A method for manufacturing a semiconductor device of the present invention includes: forming a first film, a second film and a third film in sequence on a... |
| US-7,510,979 |
Method for forming a pattern on a semiconductor device and semiconductor
device resulting from the same Disclosed are a light absorbent agent polymer for organic anti-reflective coating which can prevent diffused light reflection of bottom film layer or substrate... |
| US-7,510,978 |
Method for forming mask for using dry-etching and method for forming fine
structure pattern In the invention of this application, the resist pattern having a given pattern of opening concavity is formed on the component to be dry etched, the aqueous... |
| US-7,510,977 |
Method for manufacturing silicon carbide semiconductor device A method for manufacturing a silicon carbide (SiC) semiconductor device is disclosed that uses dry etching with the use of high-density inductive coupled plasma... |
| US-7,510,976 |
Dielectric plasma etch process with in-situ amorphous carbon mask with
improved critical dimension and etch... A plasma etch process for successively different layers, including an anti-reflection coating (ARC), an amorphous carbon layer (ACL) and a dielectric layer, with... |
| US-7,510,975 |
Method for manufacturing a semiconductor device having trenches defined in
the substrate surface In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in... |
| US-7,510,974 |
CMP process A CMP process is provided. A first polishing process on a wafer is performed using a first hard polishing pad with a first slurry. Then, a buffering process on... |
| US-7,510,973 |
Method for forming fine pattern in semiconductor device A method for forming a fine pattern in a semiconductor device is provided. In one aspect, the method can construct a fine pattern in semiconductor devices. The... |
| US-7,510,972 |
Method of processing substrate, post-chemical mechanical polishing
cleaning method, and method of and program... A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable... |
| US-7,510,970 |
Process for manufacturing semiconductor integrated circuit device In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a... |
| US-7,510,969 |
Electrode line structure having fine line width and method of forming the
same In an electrode line structure of a semiconductor device and a method for forming the same, the electrode line structure comprises a semiconductor substrate, and... |
| US-7,510,968 |
Cap for semiconductor device package, and manufacturing method thereof A cap for a semiconductor device package, including a body formed at a predetermined thickness with a cavity. The cap further includes a first seed layer formed... |
| US-7,510,967 |
Method for manufacturing semiconductor device The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a metal interconnect on a substrate; forming a refractory... |
| US-7,510,966 |
Electrically conductive line, method of forming an electrically conductive
line, and method of reducing... The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration... |
| US-7,510,965 |
Method for fabricating a dual damascene structure A method for fabricating a dual damascene structure contains providing a substrate having a conductive layer, an etching stop layer, a dielectric layer, and a... |
| US-7,510,964 |
Method for manufacturing semiconductor device that includes baking a
dielectric layer after exposure to plasma The invention is directed to a method for manufacturing semiconductor device. The method comprises steps of providing a substrate and then forming a dielectric... |
| US-7,510,963 |
Semiconductor device having multilayer interconnection structure and
manufacturing method thereof A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor... |
| US-7,510,962 |
Method for producing an anisotropic conductive film on a substrate This invention relates to a process for manufacturing an anisotropic conducting film comprising a layer of electrically insulating material and conducting... |
| US-7,510,961 |
Utilization of energy absorbing layer to improve metal flow and fill in a
novel interconnect structure A method for manufacturing an interconnect structure situated on a semiconductor wafer having a substrate assembly thereon. The interconnect structure is formed... |
| US-7,510,960 |
Bridge for semiconductor internal node A method and apparatus for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between... |
| US-7,510,959 |
Method of manufacturing a semiconductor device having damascene structures
with air gaps A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of... |
| US-7,510,958 |
Method of manufacturing a semiconductor device including a bump forming
process A method of manufacturing a semiconductor device includes an improved bump forming process. The bump forming process includes a bump forming step for forming a... |
| US-7,510,957 |
Complimentary lateral III-nitride transistors A semiconductor device which includes a laterally extending stack of laterally adjacent conductive semiconductor regions formed over a support surface of a... |
| US-7,510,956 |
MOS device with multi-layer gate stack Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by... |
| US-7,510,955 |
Method of fabricating multi-fin field effect transistor A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region is provided. The substrate... |
| US-7,510,954 |
Memory array with surrounding gate access transistors and capacitors with
global and staggered local bit lines A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access... |
| US-7,510,953 |
Integrated fet and schottky device A semiconductor device including a schottky device and a trench type semiconductor switching device such as a MOSFET formed in a common die. |
| US-7,510,952 |
Single crystalline structure, method of forming the same, semiconductor
device having the single crystalline... A single crystalline structure includes a first insulation interlayer pattern, a first epitaxial layer pattern, a second insulation interlayer pattern, and a... |
| US-7,510,951 |
Method for forming high-resolution pattern with direct writing means A patterning method comprising (a) providing a substrate having a sacrificial layer made of a first material, partially or totally formed on the substrate, (b)... |
| US-7,510,950 |
Method for manufacturing semiconductor device It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is flexible and superiority in physical strength. As... |
| US-7,510,949 |
Methods for producing a multilayer semiconductor structure Methods for producing a multilayer semiconductor structure are described. In an embodiment, the method includes providing a support substrate made of a first... |
| US-7,510,948 |
Method for producing SOI wafer Hydrogen gas is ion-implanted into a wafer for active layer via an oxide film. The wafer for active layer is bonded with a supporting wafer using the oxide film... |
| US-7,510,947 |
Method for wafer level packaging and fabricating cap structures A cap wafer with patterned film formed thereon is etched through areas not covered by the patterned film to form a plurality of openings. Then, the cap wafer is... |
| US-7,510,946 |
Method for filling of nanoscale holes and trenches and for planarizing of
a wafer surface A processing method for use in the fabrication of fabrication of nanoscale electronic, optical, magnetic, biological, and fluidic devices and structures, for... |
| US-7,510,945 |
Element formation substrate, method of manufacturing the same, and
semiconductor device A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major... |
| US-7,510,944 |
Method of forming a MIM capacitor In a method of forming MIM capacitor structure, a TiW layer is formed and a capacitor mask is used to define areas of the TiW layer that will be sued in the... |
| US-7,510,943 |
Semiconductor devices and methods of manufacture thereof A first gate dielectric of a first transistor is disposed over a workpiece in a first region, and a second gate dielectric of a second transistor is disposed... |
| US-7,510,942 |
Molecular modifications of metal/dielectric interfaces A method of increasing the work function of micro-electrodes includes providing a metal or silica surface functionalized with reactive groups and contacting the... |
| US-7,510,941 |
Semiconductor device and manufacturing method of the same The invention improves the performance of a semiconductor device. A metal silicide film is formed by a silicide process on a gate electrode and an n.sup.+-type... |
| US-7,510,940 |
Method for fabricating dual-gate semiconductor device A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the... |
| US-7,510,939 |
Microelectronic structure by selective deposition A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a... |
| US-7,510,938 |
Semiconductor superjunction structure Semiconductor structures and methods are provided for a semiconductor device (54-11, 54-12) employing a superjunction structure (81). The method comprises,... |
| US-7,510,937 |
Nonvolatile semiconductor memory device and fabrication method for the
same The fabrication method for a nonvolatile semiconductor memory device having a memory cell area including memory cells and a peripheral circuit area adjacent to... |
| US-7,510,936 |
Nonvolatile memory device and methods of fabricating and driving the same Nonvolatile memory devices and methods of fabricating and driving the same are disclosed. Disclosed devices and method comprises: growing an oxide layer on a... |
| US-7,510,935 |
Method of manufacturing a charge-trapping dielectric and method of
manufacturing a sonos-type non-volatile... In an embodiment, a method of manufacturing a charge-trapping dielectric and a silicon-oxide-nitride-oxide-silicon (SONOS)-type non-volatile semiconductor device... |
| US-7,510,934 |
Methods of fabricating nonvolatile memory devices A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate... |
| US-7,510,933 |
Fabrication method of semiconductor integrated circuit device Provided is a fabrication method of a semiconductor integrated circuit device, which comprises disposing, in a ultrapure water preparing system, UF equipment... |
| US-7,510,932 |
Semiconductor devices having a field effect transistor and methods of
fabricating the same A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device... |
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