Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,525,852 |
Nonvolatile memory For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be... |
| US-7,525,851 |
Row decoder circuit and related system and method A row decoder circuit is described of the type comprising at least one input stage connected to a first supply voltage reference and to an output stage connected... |
| US-7,525,850 |
Multi-level nonvolatile semiconductor memory device and method for reading
the same A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of... |
| US-7,525,849 |
Flash memory with sequential programming A method of programming a group of memory cells in a semiconductor memory device selecting a group of memory cells for programming, and enabling a first subgroup... |
| US-7,525,848 |
Method for erasing and changing data of floating gate flash memory A method for erasing data stored in the memory cells of the floating gate flash memory is included. The method allows a plurality of sectors to be disposed in a... |
| US-7,525,847 |
Semiconductor device and methods of manufacturing the same A semiconductor device includes at least two transistors and a charge-trapping structure. The charge-trapping structure traps charges, which are moved from a... |
| US-7,525,846 |
Memory device A memory device includes a memory cell having a capacitor for accumulating electric charges in accordance with the logic of data, a bit line connected to the... |
| US-7,525,845 |
Non-volatile semiconductor storage device In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite... |
| US-7,525,844 |
Semiconductor memory device with MOS transistors each having floating gate
and control gate and method of... A semiconductor memory device includes a memory cell array, first bit lines, second bit lines, first sense amplifiers and second sense amplifiers. The memory... |
| US-7,525,843 |
Non-volatile storage with adaptive body bias A non-volatile storage system in which body bias can be applied to optimize performance. Body bias can be set in an adaptive manner to reduce an error count of... |
| US-7,525,842 |
Increased NAND flash memory read throughput A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and... |
| US-7,525,841 |
Programming method for NAND flash A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells... |
| US-7,525,840 |
Memory array with pseudo single bit memory cell and method In the multi level/bit per cell memory array, a flag cell indicates pseudo single bit per cell configuration for one or more cells of the memory array. The... |
| US-7,525,839 |
Semiconductor memory device capable of correcting a read level properly In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit... |
| US-7,525,838 |
Flash memory device and method for programming multi-level cells in the
same A method for programming a flash memory device is provided, where the flash memory device includes a plurality of memory cells, and where a threshold voltage of... |
| US-7,525,837 |
Magnetoresistive effect element and magnetic memory A magnetoresistive effect element includes a nonmagnetic layer having mutually facing first and second surfaces. A reference layer is provided on the first... |
| US-7,525,836 |
Non-imprinting memory with high speed erase A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the... |
| US-7,525,835 |
Method and apparatus for reduced power cell The invention relates to reduced power cells. Some embodiments of the invention provide a memory circuit that has a storage cell. The storage cell contains... |
| US-7,525,834 |
SRAM cell structure and circuits An SRAM circuit structure and method for reducing leakage currents and/or increasing the speed of the devices. Various forms of SRAM devices may be fabricated... |
| US-7,525,833 |
Nanoscale shift register and signal demultiplexing using
microscale/nanoscale shift registers One embodiment of the present invention is a nanoscale shift register that can be used, in certain nanoscale and mixed-scale logic circuits, to distribute an... |
| US-7,525,832 |
Memory device and semiconductor integrated circuit First electrode layer includes a plurality of first electrode lines (W1, W2) extending parallel to each other. State-variable layer lying on the first electrode... |
| US-7,525,831 |
Method for improving sensing margin of electrically programmable fuses A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference... |
| US-7,525,830 |
Nonvolatile ferroelectric perpendicular electrode cell, FeRAM having the
cell and method for manufacturing the cell A nonvolatile ferroelectric perpendicular electrode cell comprises a ferroelectric capacitor and a serial PN diode switch. The ferroelectric capacitor includes a... |
| US-7,525,829 |
Semiconductor storage device A semiconductor storage device that is capable of utilizing dummy cells effectively and enhancing the memory cell density. Every second row of bit lines (second... |
| US-7,525,828 |
Semiconductor memory device and redundancy method thereof A semiconductor memory device including a first memory to which a first address and first input data are input, and which outputs first output data, a... |
| US-7,525,827 |
Stored don't-care based hierarchical search-line scheme In the proposed stored don't-care hierarchical search-line scheme, a content-addressable memory (CAM) is divided into several blocks. Each block contains a... |
| US-7,525,826 |
Switching power supply apparatus and method Configurations provide reduction in the hum and the weak shocks that are produced in audio equipments where electrical power is supplied. Switching electrical... |
| US-7,525,825 |
Snap in high power, high current connector with integrated EMI filtering A filter assembly is provided which includes a Faraday cage interface. Electrical noise is filtered by the Faraday cage interface. The Faraday cage interface is... |
| US-7,525,824 |
Method to control a frequency converter A method for the control of a static frequency converter, in which an alternating voltage provided by a generator with a first frequency is first rectified in a... |
| US-7,525,823 |
Switch mode power supply systems Methods and apparatus for sensing the output current in a switch mode power supply (SMPS) using primary side sensing are described. A system includes a primary... |
| US-7,525,822 |
DC converter including a tertiary winding for driving synchronous
rectifiers A DC converter has a transformer with loosely coupled primary and secondary windings, a main switch connected in series with the primary winding of the... |
| US-7,525,821 |
Power supply system and apparatus The present invention relates to a switched mode power supply with programmable digital control and to a power supply system comprising a plurality of switched... |
| US-7,525,820 |
Inverter Primary and secondary regions are electrically insulated from each other. The first and second pulse transformers are provided to the respective transistors in... |
| US-7,525,819 |
Switching mode power supply and method for generating a bias voltage A switching mode power supply and method for generating a bias voltage is described. The bias voltage is generated by using a current source coupled to a primary... |
| US-7,525,818 |
Memory card connector with EMI shielding A memory card connector assembly for use within a chassis includes a conductive shell that has a forward perimeter. A connector including a dielectric housing... |
| US-7,525,817 |
Wiring layout of auxiliary wiring package and printed circuit wiring board A printed circuit board wiring system including a printed wiring circuit board having a plurality of conductive layers, at least one electronic part mounted on... |
| US-7,525,816 |
Wiring board and wiring board connecting apparatus The present invention provides a wiring board including a first board provided with a first wiring pattern and a second board provided with a second wiring... |
| US-7,525,815 |
Device for assemblying transversal PCI expansion cards and a computer
housing A device for assembling transversal PCI expansion cards and a computer housing includes a vertical connection board which is installed in an internal space of a... |
| US-7,525,814 |
Wiring board and method for manufacturing the same A wiring board includes a plurality of via pads disposed on a ceramic sub-core accommodated in a core board. A Cu-plated layer is formed on the surface of a... |
| US-7,525,813 |
Semiconductor device In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on... |
| US-7,525,812 |
Chip carrier and fabrication method A substrate having a ground plane, a first side, and a second side is provided. A via that electrically connects the first side to the second side is formed. A... |
| US-7,525,811 |
Retention device for securing expansion card shields A retention device for securing expansion card shields (30) includes a chassis (10), and a lock member (20) for securing the expansion card shields to the... |
| US-7,525,810 |
Connector fixing structure and electronic apparatus According to one embodiment, a connector fixing structure includes a printed circuit board assembly, and a base to which the printed circuit board assembly is... |
| US-7,525,809 |
Isolated control and network wireway for motor control center A packaged electrical system includes an enclosure and a main interior volume for component supports. The component supports may support electrical, electronic,... |
| US-7,525,808 |
Device, system, and method of flexible hardware connectivity Device, system, and method of flexible hardware connectivity. For example, a Printed Circuit Board (PCB) system includes: a rigid platform having embedded... |
| US-7,525,807 |
Semiconductor memory device A semiconductor memory device according to the present invention comprises a housing including a card bus connector for connection to a host device and having a... |
| US-7,525,806 |
Combination current sensor and relay A combination current sensor and relay has an improved housing. In one aspect, the housing includes light emitting diodes on an upper surface that indicate open... |
| US-7,525,805 |
Electronic apparatus An electronic apparatus includes a housing, a first unit that is attached through a front side of the housing, a second unit that is attached through a backside... |
| US-7,525,804 |
Semiconductor device and method of manufacturing the same A semiconductor package is provided with a low thermal conductivity plate that covers an entire upper surface of a heat dissipating component, by which heat... |
| US-7,525,803 |
Power converter having multiple layer heat sinks A power converter including a printed circuit board (PCB) having a plurality of heat conductive layers configured to sink heat generated by the power converter... |
Copyright 2008−2012 Patents.com
