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| Patent # | Description |
|---|---|
| US-7,526,711 |
Decoding method and device for repeatedly decoding first and second
encoded data A decoding device according to the one embodiment of the invention includes: a first decoder performing a first decoding based on first encoded data obtained by... |
| US-7,526,710 |
Recording format for information date, information recording/reproducing
cording circuit An efficient encoding method is provided for error correction coding in high density magnetic recording/reproducing apparatus. A first encoding circuit applies a... |
| US-7,526,709 |
Error detection and correction in a CAM An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not... |
| US-7,526,708 |
Adaptive retransmission for frequency spreading A method and corresponding wireless communication equipment, for use for example in connection with automatic retransmission request protocols for orthogonal... |
| US-7,526,707 |
Method and apparatus for encoding and decoding data using a pseudo-random
interleaver A pseudo-random bit interleaver and de-interleaver comprising a source for generating pseudo-random numbers and transformation logic that transforms each... |
| US-7,526,706 |
Method and apparatus for preventing network outages A computer implemented method, apparatus, and computer usable program code to determine whether an acknowledgment packet from an end point acknowledges receipt... |
| US-7,526,705 |
Acknowledgement message modification in communication networks A method for processing a received encoded data unit comprises: decoding the received encoded data unit; determining whether the encoded data unit has been... |
| US-7,526,704 |
Testing system and method allowing adjustment of signal transmit timing A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing... |
| US-7,526,703 |
Method of test pattern generation in IC design simulation system The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors... |
| US-7,526,702 |
Method and system for testing a random access memory (RAM) device having
an internal cache A method for testing an internal bus of a random access memory ("RAM") device, the RAM device having an internal cache coupled to a memory array by the internal... |
| US-7,526,701 |
Method and apparatus for measuring group delay of a device under test A method of measuring group delay of a device under test is provided. The method includes the steps of providing an analog input signal with a predetermined... |
| US-7,526,700 |
Semiconductor integrated circuit device Provided are external input/output signal terminals, an interface circuit including a plurality of unit input/output circuits accompanying the respective signal... |
| US-7,526,699 |
Method for creating a built-in self test (BIST) table for monitoring a
monolayer deposition (MLD) system A method of monitoring a processing system in real-time using low-pressure based modeling techniques that include processing one or more of wafers in a... |
| US-7,526,698 |
Error detection and correction in semiconductor structures A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip.... |
| US-7,526,697 |
Memory test circuit and method To test memories operating with different operational clocks and deal with a delay involved in testing a memory at a physically remote location. A memory test... |
| US-7,526,696 |
Scan-based self-test structure and method using weighted scan-enable
signals A scan-based self-test architecture and method using weighted scan enable signals is disclosed. The self-test architecture comprises: a linear feedback shift... |
| US-7,526,695 |
BIST with generator, compactor, controller, adaptor, and separate scan
paths A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106,and controller 110 remain the same as in the known... |
| US-7,526,694 |
Integrated circuit internal test circuit and method of testing therewith A test circuit in an integrated circuit and method of testing therewith are described. A test pattern generator provides a test pattern. A reference circuit... |
| US-7,526,693 |
Initial decision-point circuit operation mode A circuit that includes a controller and at least one control I/O pin. When the controller is placed into an initial state, the controller initializes the... |
| US-7,526,692 |
Diagnostic interface architecture for memory device A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized... |
| US-7,526,691 |
System and method for using TAP controllers A system and method for dynamically writing to and reading from an internal register space of a chip using a TAP controller without interfering with the normal... |
| US-7,526,690 |
Semiconductor device-testing apparatus A semiconductor device-testing apparatus which is capable of testing semiconductor devices simultaneously by a simple construction. A plurality of latch circuits... |
| US-7,526,689 |
Testing address lines of a memory controller All the address lines in a data processing system can be tested by using one or more small memory device that do not occupy the full addressing capability of the... |
| US-7,526,688 |
Parallel bit testing device and method A memory device includes a memory cell array to store data, a register to store test data, and a decision circuit to invert the test data and to determine a... |
| US-7,526,687 |
Turbo code interleaver with near optimal performance A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers... |
| US-7,526,686 |
Apparatus, system, and method for active data verification in a storage
system An apparatus, system and method of verifying data are provided. Active data are identified among data on a storage device, records the location of the active... |
| US-7,526,685 |
Application manager for monitoring and recovery of software based
application processes A constant monitoring and recovery system that enables the measurement of task usage/metrics and performance of software-based business applications. These... |
| US-7,526,684 |
Deterministic preventive recovery from a predicted failure in a
distributed storage system A data storage subsystem in a distributed storage system having a plurality of predictive failure analyzing data storage devices. The subsystem furthermore has a... |
| US-7,526,683 |
Dynamic self-tuning soft-error-rate-discrimination for enhanced
availability of enterprise computing systems A method for use in a computer system provides a dynamic, "self tuning" soft-error-rate-discrimination (SERD) method and apparatus. Specially designed SRAMs or... |
| US-7,526,682 |
Effective diagnosis of software hangs One aspect of the present invention involves storing the operating time offset of a thread within an area of memory of the thread, and storing a load time and a... |
| US-7,526,681 |
Software testing framework A software testing framework is described. In one embodiment, the software testing framework is run on a client-side computer system and provides the user an... |
| US-7,526,680 |
Stress testing a website having a backend application Execution of a test scenario is managed where the test scenario is for testing a website deployment having a server in communication with a backend application.... |
| US-7,526,679 |
Apparatus for developing and verifying system-on-chip for internet phone Provided is an apparatus for developing and verifying a system-on-chip for an Internet phone. The object of the present invention is to provide the ... |
| US-7,526,678 |
Methods, systems, and products for verifying integrity of web-server
served content Methods, systems, and products are disclosed for verifying the integrity of web server content. Communication with a server is initiated and content is retrieved... |
| US-7,526,677 |
Fragility handling A method is provided for handling failures in a computer system including a compliance checking system in a computer network. In response to a client computer... |
| US-7,526,676 |
Slave device having independent error recovery A slave device adapted to couple to a master processor and including an error handler and a communication controller. The error handler is configured to detect... |
| US-7,526,675 |
Software recovery method for flash media with defective formatting A method and software program for recovering data from corrupted flash media. In one aspect, the method employs a low-level access scheme that enables data to be... |
| US-7,526,674 |
Methods and apparatuses for supplying power to processors in multiple
processor systems Methods and apparatuses for supplying power to processors in multiple processor systems are disclosed. Embodiments comprise a method of monitoring a parameter... |
| US-7,526,673 |
Parallel processing system by OS for single processors and parallel
processing program In a parallel processing system by an OS for single processors which operates an OS for single processors and an existing application for single processors on a... |
| US-7,526,672 |
Mutual exclusion techniques in a dynamic peer-to-peer environment Mutual exclusion techniques for use in a dynamic peer-to-peer environment are described. In an implementation, a method includes receiving, at each of a... |
| US-7,526,671 |
Network communication system The network communication system is capable of communicating with many internal units at high speed, improving reliability of the system and decreasing a... |
| US-7,526,670 |
Method and system to monitor a diverse heterogeneous application
environment A method to detect potential problems within a heterogeneous and diverse application environment. Operations data is received from a plurality of application... |
| US-7,526,668 |
Failover method of remotely-mirrored clustered file servers By incorporating a referral mechanism, a failover method and system for remotely mirrored clustered file servers enables a client computer to transparently... |
| US-7,526,667 |
Error reporting and correcting method for peripheral An error reporting and correcting method applied to a peripheral. The peripheral can be connected to the user terminal via the network. In the error reporting... |
| US-7,526,666 |
Derived clock synchronization for reduced skew and jitter Two or more circuits (e.g. processing cores of a graphics processor) operate synchronously at a fast clock frequency. A core interface to each of the processing... |
| US-7,526,665 |
Electrically controlled suspension system An electronically controlled suspension system according to the present invention comprises a sensor unit for extracting and providing a vertical acceleration... |
| US-7,526,664 |
Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a... |
| US-7,526,663 |
Method and apparatus for reducing the power consumed by a computer system A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power... |
| US-7,526,662 |
Method and apparatus for secure module restoration A method and apparatus is provided for power conservation of a hardware module (142) which is coupleable to a portable electronic device (100). The hardware... |
| US-7,526,661 |
Performance state-based thread management Systems and methods of managing threads provide for selecting a thread for execution and identifying a target performance state of a processor core based on the... |
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