Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,533,322 |
Method and system for performing function-specific memory checks within a
vehicle-based control system Integrity of data stored in a memory space associated with a vehicle-based control system (such as a traction enhancement system) is verified through the use of... |
| US-7,533,321 |
Fault tolerant encoding of directory states for stuck bits A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error... |
| US-7,533,320 |
Wireless transmit/receive unit having a turbo decoder with circular
redundancy code signature comparison and method An iterative turbo decoder for a wireless transmit receive unit (WTRU) of a wireless communication system and method for error correcting received communication... |
| US-7,533,319 |
Apparatus and method for recording and/or reproducing data on an
information storage medium using padding... An apparatus and method for recording and/or reproducing data on a disc using padding information, and a corresponding information storage medium. The recording... |
| US-7,533,318 |
Test pattern generator and test pattern generation method for onboard
memory devices A test pattern generator generating a test pattern for performance testing of an onboard memory is provided for a device having a memory macro, a serial input... |
| US-7,533,317 |
Serializer/deserializer circuit for jitter sensitivity characterization Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ... |
| US-7,533,316 |
Method and apparatus for disabling and swapping cores in a multi-core
microprocessor In some embodiments, a method and apparatus for disabling and swapping cores in a multi-core microprocessor are presented. In this regard, a test agent is... |
| US-7,533,315 |
Integrated circuit with scan-based debugging and debugging method thereof An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is... |
| US-7,533,314 |
Unit test extender A unit test extending system and method use a unit test extender engine and a test pattern to extend a unit test written to validate code under test. The unit... |
| US-7,533,313 |
Method and apparatus for identifying outlier data A method for converting data includes generating a first data vector of data measurements related to processing of at least one workpiece. Each element of the... |
| US-7,533,312 |
System and method for testing of electronic circuits The system and method of the present invention combine multiple tests (15) into a batch and submit the batch for processing to exercise electronic circuits, for... |
| US-7,533,311 |
Programmable management IO pads for an integrated circuit A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another... |
| US-7,533,310 |
Semiconductor memory test device and method thereof A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at... |
| US-7,533,309 |
Testing memories using algorithm selection A method of performing a built-in-self-test (BIST) of at least one memory element of a circuit is disclosed. In a specific example, a determination is made... |
| US-7,533,308 |
Semiconductor test system The semiconductor test system comprises a test device for testing semiconductor devices including redundant circuits to obtain fail information of defective... |
| US-7,533,307 |
Method and circuit arrangement for operating a volatile random access
memory as a detector A method for operating a volatile random access memory as a detector, with predetermined information being stored in at least one area of the volatile random... |
| US-7,533,306 |
Turbo decoding apparatus and interleave-deinterleave apparatus In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a... |
| US-7,533,305 |
Method and apparatus for structured detection and handling of problems
occurring in a computerized system In a method and apparatus for structured detection and handling of problems occurring in a computerized system, data storage contains multiple data sets, each... |
| US-7,533,304 |
Method and system of signal noise reduction A method and system of signal noise reduction used for digital chips to prevent errors when signal noise occurs includes checking whether a recent received... |
| US-7,533,303 |
Method and system for performing system-level correction of memory errors A method and system for correcting errors in a memory subsystem in a computer system. Occurrence of correctable memory errors are monitored and a determination... |
| US-7,533,302 |
Trace and debug method and system for a processor A trace and debug method and system for a processor. The method includes the steps: (A) monitoring a program counter (PC); (B) determining if a processor core... |
| US-7,533,301 |
High level operational support system A high level Operational Support System (OSS) framework provides the infrastructure and analytical system to enable all applications and systems to be managed... |
| US-7,533,300 |
Configurable error handling apparatus and methods to operate the same Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package,... |
| US-7,533,299 |
Temporal correlation of messages transmitted by a microprocessor
monitoring circuit The invention concerns a method for transmitting digital messages through output terminals (22) of a monitoring circuit (18) integrated to a microprocessor (12),... |
| US-7,533,298 |
Write journaling using battery backed cache A system, apparatus and method for maintaining information related to a write operation is described. In one embodiment of the invention, a write journal is... |
| US-7,533,297 |
Fault isolation in a microcontroller based computer A method and data processing system for isolating a faulty component in a computer. A first microcontroller detects a fault in a component of a computer.... |
| US-7,533,296 |
Method for optimizing the transmission of logging data in a multi-computer
environment and a system... This invention relates to a method for the transmission of logging data, from a primary node to a secondary node within a cluster of computers. The method... |
| US-7,533,295 |
Two node virtual shared disk cluster recovery A method for recovery in a two-node data processing system is provided wherein each node is a primary server for a first nonvolatile storage device and for which... |
| US-7,533,294 |
Functional coverage driven test generation for validation of pipelined
processors A functional coverage based test generation technique for pipelined architectures is presented. A general graph-theoretic model is developed that can capture the... |
| US-7,533,293 |
Systems and methods for CPU repair In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU... |
| US-7,533,292 |
Management method for spare disk drives in a raid system A RAID system employs a storage controller, a primary storage array having a plurality of primary storage units, and a spare storage pool having one or more... |
| US-7,533,291 |
System and method for storing a data file backup A method for storing a data file copy is provided. The method includes the steps of: (a) dividing a duplicate of a data file stored in a mother node into a... |
| US-7,533,290 |
Microcode updating error handling apparatus and method thereof A method of microcode updating error handling for an electronic device is disclosed. The method includes: providing a status flag to indicate if updating a... |
| US-7,533,289 |
System, method, and computer program product for performing live cloning A method for cloning a running component from a first machine to a second machine is provided. The method includes: iteratively coping a state of the running... |
| US-7,533,288 |
Method of achieving high reliability of network boot computer system In a network computer system, recovery may be impossible from a fault when the fault occurs in a network switch in a network or a device such as an external disk... |
| US-7,533,287 |
Method for processing a connection-mode IP connection according to
non-availability situations A method for processing a connection-mode IP connection is provided. Generic methods known from the prior are problematic in that in the case of connection-mode... |
| US-7,533,286 |
Regulating application of clock to control current rush (DI/DT) In general, in one aspect, the disclosure describes an apparatus for engineering di/dt. The apparatus includes a plurality of functional blocks to perform... |
| US-7,533,285 |
Synchronizing link delay measurement over serial links Systems, methods, and other embodiments associated with synchronizing link delay is provided. In one example system, a system for synchronizing signal... |
| US-7,533,284 |
System for controlling an operation state of a portable computer based on
detected temperature of an external... A temperature control system used in a portable computer comprises a first control part, a second control part connected to an operation processing unit (OPU), a... |
| US-7,533,283 |
Apparatus and method for modular dynamically power managed power supply
and cooling system for computer... Network architecture, computer system and/or server, circuit, device, apparatus, method, and computer program and control mechanism for managing power... |
| US-7,533,282 |
Logic circuit apparatus for selectively assigning a plurality of circuit
data to a plurality of programmable... A logic circuit apparatus includes a plurality of programmable logic circuits, a circuit data memory, a control unit. The plurality of programmable logic... |
| US-7,533,281 |
Method and system for controlling powers of a plurality of servers A method and system of controlling powers of a plurality of servers with a power control command mechanism. The system for controlling powers of a plurality of... |
| US-7,533,280 |
Emergency call apparatus and method for smart phone An emergency call apparatus and method for a smart phone are disclosed in which the apparatus includes a personal data assistant unit including a telephone power... |
| US-7,533,279 |
Remote control save and sleep override A method is presented that handles a power down signal received by a device. Other types of signals, such as suspend or save and sleep, may also be handled. A... |
| US-7,533,278 |
Electronic device and power saving control method According to one embodiment, an EC/KBC reads data of an acceleration sensor. The EC/KBC determines whether a computer is in a top heat state. If the EC/KBC... |
| US-7,533,277 |
Operating system shut down A user interface and scheme is provided for facilitating shutting down an operating system. A shut down command is initiated in an operating system, and... |
| US-7,533,276 |
Program execution device A program execution device capable of protecting a program against unauthorized analysis and alteration is provided. The program execution device includes an... |
| US-7,533,275 |
Data processing apparatus and memory card using the same A CPU and a memory are connected to each other through an address bus, a data bus, a read signal line and a write signal line. A read control signal and a write... |
| US-7,533,274 |
Reducing the boot time of a TCPA based computing system when the core root
of trust measurement is embedded in... A method, computer program product and system for reducing the boot time of a TCPA based computing system. A flash memory in the TCPA based computing system may... |
| US-7,533,273 |
Method and system for controlling an encryption/decryption engine using
descriptors Controlling an encryption/decryption device using descriptors may include formatting a first block of memory to contain a generic data template used to control... |
Copyright 2008−2012 Patents.com
