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| Patent # | Description |
|---|---|
| US-7,533,272 |
System and method for certifying that data received over a computer
network has been checked for viruses A system, method, and computer program product are provided for certifying that data transferred from a first computer to a recipient computer is free from... |
| US-7,533,271 |
Method and apparatus for remote control and monitoring of a multimedia
system A method and apparatus for remote control and/or monitoring of a multimedia system includes processing that begins when a hand held device transmits a remote... |
| US-7,533,270 |
Signature schemes using bilinear mappings Methods and systems are provided for generating and verifying signatures of digital messages communicated between signers and verifiers. Using bilinear mappings,... |
| US-7,533,269 |
Digital-signed digital document exchange supporting method and information
processor In response to a sign request including a digital document from a document-creating device 10, a digital-signed-document exchange supporting server 30... |
| US-7,533,268 |
Digital signature with an embedded view Digital signatures having an embedded view of signed data that lock the signed data but permit it to be repurposed are described. One of these digital signatures... |
| US-7,533,267 |
Anti-tampering signature method for rewritable media, anti-tampering
signature apparatus for executing the... An anti-tampering signature apparatus is provided with an extraction portion 33 for extracting a characteristic quantity that represents a characteristic of... |
| US-7,533,266 |
Watermark-based access control method and device A method of controlling access to a resource using a verifying device uses watermarking device that embeds an authorization code in a signal using watermarking... |
| US-7,533,265 |
Establishment of security context The present invention provides for maintaining security context during a communication session between applications, without having to have executable code in... |
| US-7,533,264 |
Custom security tokens A sending computer system generates a message and creates one or more security tokens to encrypt portions of the message. The computer system includes in the... |
| US-7,533,263 |
System and method for registering a subscriber station on the packet
service call state control function CSCF... The aim of the invention is to provide a particularly simple means of authentication and/or authorization of a station (MS) for the connection and/or service... |
| US-7,533,262 |
Media data protection A data protection portion includes the file system alteration checking portion. One aspect of the file system alteration checking portion relates to a media... |
| US-7,533,261 |
Method and apparatus for encoding and storing session data Session data is encoded in a tag-length-value format and encrypted using a modified encryption key. A session cookie, formed by concatenating the length of the... |
| US-7,533,260 |
Method and apparatus for encoding and storing session data Session data is encoded in a tag-length-value format and encrypted using a modified encryption key. A session cookie is then formed by concatenating the length... |
| US-7,533,259 |
Encapsulation of secure encrypted data in a deployable, secure
communication system allowing benign, secure... Sensitive, Type 1 KIV-encrypted data is encapsulated into IP packets in a remotely deployed, secure communication system. The IP packets are addressed to a... |
| US-7,533,258 |
Using a network-service credential for access control Methods and devices for controlling access to a service over a network are described. A credential is provided to a device. The credential indicates the device... |
| US-7,533,257 |
Server authentication verification method on user terminal at the time of
extensible authentication protocol... A server certificate verification method in a terminal during. Extensible Authentication Protocol authentication for Internet access is provided, the method... |
| US-7,533,256 |
Method and apparatus for encryption of data on storage units using devices
inside a storage area network fabric The capability to encrypt or compress the traffic over network links, thus improving the security of the link on the performance of the links, and the capability... |
| US-7,533,255 |
Method and apparatus for restricting address resolution protocol table
updates A method of restricting Address Resolution Protocol (ARP) table updates to updates originating from authorized subsystems is disclosed. According to one aspect... |
| US-7,533,254 |
Volatile memory persistence during warm reboot in an optical transceiver An operational optical transceiver configured to preserve a portion of volatile memory during a warm reboot process. The optical transceiver includes a... |
| US-7,533,253 |
System and method for fetching a boot code A multi-chip system and a boot code fetch method include a nonvolatile memory chip storing a volatile memory chip, and a boot code, and a host fetching the boot... |
| US-7,533,252 |
Overriding a static prediction with a level-two predictor In one embodiment, the present invention includes a method for determining if an entry corresponding to a prediction address is present in a first predictor, and... |
| US-7,533,251 |
Semiconductor integrated circuit, development support system and execution
history tracing method When a call instruction or interrupt branch is executed by a CPU, its return address is pushed to a stack memory. When a return instruction is executed, the... |
| US-7,533,250 |
Automatic operand load, modify and store A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled... |
| US-7,533,249 |
Reconfigurable integrated circuit, circuit reconfiguration method and
circuit reconfiguration apparatus In order to reuse configuration information in a dynamic reconfiguration arithmetic circuit, data lines, address lines, a mask register and the like are required... |
| US-7,533,248 |
Multithreaded processor including a functional unit shared between
multiple requestors and arbitration therefor A multithreaded processor including a shared functional unit. In one embodiment, the multithreaded processor includes a functional unit coupled to a... |
| US-7,533,247 |
Operation frame filtering, building, and execution The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a... |
| US-7,533,246 |
Application program execution enhancing instruction set generation for
coprocessor and code conversion with... A method for automatically configuring a microprocessor architecture so that it is able to efficiently exploit instruction level parallelism in a particular... |
| US-7,533,245 |
Hardware assisted pruned inverted index component An optimized document-indexing device is based on a pruned inverted index structure mapped to hardware. The device can be accommodated on a single chip and can... |
| US-7,533,244 |
Network-on-chip dataflow architecture Network-on-Chip Dataflow Architecture is the new microprocessor architecture. It consists of many processing elements connecting together via two distinct... |
| US-7,533,243 |
Processor for executing highly efficient VLIW A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field... |
| US-7,533,242 |
Prefetch hardware efficiency via prefetch hint instructions A software agent assembles prefetch hint instructions or prefixes defined in an instruction set architecture, the instructions/prefixes conveying prefetch hint... |
| US-7,533,241 |
Variable size cache memory support within an integrated circuit An integrated circuit 2 is provided with a cache memory 6 and a cache controller 10 coupled to the cache memory 6 via a cache memory interface 8. The cache... |
| US-7,533,240 |
Device with mapping between non-programmable and programmable memory A memory storage device connectable to a bus comprises a first memory module that stores data, a second memory module that is capable of being programmed, and a... |
| US-7,533,239 |
System and method for dynamic sizing of cache sequential list A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space... |
| US-7,533,238 |
Method for limiting the size of a local storage of a processor A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage... |
| US-7,533,237 |
Off-chip memory allocation for a unified shader Systems and methods for dynamically allocating memory for thread processing may reduce memory requirements while maintaining thread processing parallelism. A... |
| US-7,533,236 |
Off-chip out of order memory allocation for a unified shader Systems and methods for dynamically allocating memory for thread processing may reduce memory requirements while maintaining thread processing parallelism. A... |
| US-7,533,235 |
Reserve stacking The reserves of a flexible volume and the aggregate which contains the flexible volume are "stacked". When the flexible volume is created, a portion of the... |
| US-7,533,234 |
Method and apparatus for storing compressed code without an index table A method and apparatus is described herein for compressing a binary image in memory and decompressing a portion memory in response to a request, without using a... |
| US-7,533,233 |
Accommodating multiple operating systems and memory sizes on IA-32
platforms A method of configuring IA-32 computer resources accommodates multiple operating systems and memory sizes automatically. If total available physical memory does... |
| US-7,533,232 |
Accessing data from different memory locations in the same cycle In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the... |
| US-7,533,231 |
Method and circuit for increasing the memory access speed of an enhanced
synchronous memory A memory and method for operating it provide for increased data access speed. In an implementation, a synchronous memory or SDRAM includes a central memory... |
| US-7,533,230 |
Transparent migration of files among various types of storage volumes
based on file access properties In one embodiment, a method and system for storing a file in a storage domain is provided. The method includes monitoring access to a file to determine a file... |
| US-7,533,229 |
Disaster recovery and backup using virtual machines One or more computer systems, a carrier medium, and a method are provided for backing up virtual machines. The backup may occur, e.g., to a backup medium or to a... |
| US-7,533,228 |
Two-pass sliding compaction During two-pass sliding compaction, a heap may first be logically divided into fixed-sized segments, or chunks, and information regarding each chunk, known as... |
| US-7,533,227 |
Method for priority scheduling and priority dispatching of store
conditional operations in a store queue A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete... |
| US-7,533,226 |
Data processor memory circuit A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first... |
| US-7,533,225 |
Method and apparatus for enabling adaptive endianness A method for reading a block, involving receiving a request to obtain the block, wherein the request comprises a block pointer, determining a block endianness by... |
| US-7,533,224 |
Apparatus, method and computer program for content utilization management A processing device, processing method, and information recording medium manages copyright and utilization control of each of fragmented data of contents stored... |
| US-7,533,223 |
System and method for handling memory requests in a multiprocessor shared
memory system A system and method are provided for tracking memory requests within a data processing system. The system includes a request tracking circuit that is coupled to... |
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