Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,535,775 |
Page buffer and a method for driving the same in a nonvolatile memory
device A page buffer may comprise of a latch connected to a sense node at a first contact point. The page buffer may also comprise of a sensing circuit connected to the... |
| US-7,535,774 |
Circuit for generating an internal enabling signal for an output buffer of
a memory A circuit is for generating an internal enabling signal for the output buffer of a memory as a function of external commands for enabling the memory and for... |
| US-7,535,773 |
Data output buffer whose mode switches according to operation frequency
and semiconductor memory device having... A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit.... |
| US-7,535,772 |
Configurable data path architecture and clocking scheme Data paths (100 and 900) can be configured to accommodate two or four burst data sequences, with a data value being input/output each half clock cycle. A data... |
| US-7,535,771 |
Devices and methods to improve erase uniformity and to screen for marginal
cells for NROM memories A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory... |
| US-7,535,770 |
Flash memory device with reduced drain stresses A memory device includes a matrix of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a transistor having a... |
| US-7,535,769 |
Time-dependent compensation currents in non-volatile memory read
operations Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge... |
| US-7,535,768 |
Method of controlling copy-back operation of flash memory device including
multi-level cells A method of controlling a copy-back operation of a flash memory device including multi-level cells. In the method, the copy-back operation can be executed even... |
| US-7,535,767 |
Reading multi-cell memory devices utilizing complementary bit information Providing differentiation between overlapping memory cell bits in multi-cell memory devices is described herein. By way of example, select groups of memory cells... |
| US-7,535,766 |
Systems for partitioned soft programming in non-volatile memory Soft programming is performed to narrow the threshold voltage distribution of a set of erased memory cells. Soft programming can shift the threshold voltage of... |
| US-7,535,765 |
Non-volatile memory device and method for reading cells A non-volatile device and method of operating the device including changing a read reference level for reading a group of memory cells as a function of changes... |
| US-7,535,764 |
Adjusting resistance of non-volatile memory using dummy memory cells In some non-volatile storage systems, a block of data memory cells is manufactured with a dummy word line at the bottom of the block, at the top of the block,... |
| US-7,535,763 |
Controlled boosting in non-volatile memory soft programming A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be... |
| US-7,535,762 |
Semiconductor memory device A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first... |
| US-7,535,761 |
Flash memory device capable of preventing coupling effect and program
method thereof The present invention provides a flash memory device that includes a word line; even page cells that are physically adjacent and connected to the word line; and... |
| US-7,535,760 |
Memory devices and memory systems having the same A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality... |
| US-7,535,759 |
Memory system with user configurable density/performance option The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple... |
| US-7,535,758 |
One or multiple-times programmable device Methods and apparatus, including computer program products, for a one or multiple-times programmable memory device. A semiconductor may include an active region... |
| US-7,535,757 |
Magnetic memory To provide a magnetic memory capable of reducing the amount of write current, even when the element size is 0.7 .mu.m or less. Each of storage areas has a... |
| US-7,535,756 |
Method to tighten set distribution for PCRAM A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for... |
| US-7,535,755 |
Magnetic memory device and method for fabricating the same The magnetic memory device includes a magnetic shield film 48, and a magnetoresistive effect element 62 formed over the magnetic shield film 48 and including a... |
| US-7,535,754 |
Integrated circuit memory devices with MRAM voltage divider strings
therein A memory device and method of reading the memory device is disclosed. The memory device includes a first string of MRAM cells and a second string of MRAM cells.... |
| US-7,535,753 |
Semiconductor memory device A semiconductor memory device includes a first inverter circuit and a second inverter circuit, a first transfer gate which is connected between a first power... |
| US-7,535,752 |
Semiconductor static random access memory device According to an aspect of the invention there is provided a semiconductor memory device, including a first inverter being composed of a first P-channel MOS... |
| US-7,535,751 |
Dual-port SRAM device A dual-port SRAM cell structure includes a first inverter area where a first inverter is constructed on a semiconductor substrate; a second inverter area where a... |
| US-7,535,750 |
Asymmetrical random access memory cell, and a memory comprising
asymmetrical memory cells Asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of... |
| US-7,535,749 |
Dynamic memory word line driver scheme A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater... |
| US-7,535,748 |
Semiconductor memory device A memory cell is constructed by connecting in series a variable-resistance element having a resistance which is varied by application of a positive voltage to... |
| US-7,535,747 |
Phase change random access memory and related methods of operation In a phase change random access memory (PRAM) device, data is programmed in selected memory cells using a plurality of program loops. In each program loop,... |
| US-7,535,746 |
Nonvolatile semiconductor memory device and read method A nonvolatile semiconductor memory device according to the present invention comprises a memory cell selecting circuit for selecting the memory cell from the... |
| US-7,535,745 |
Ferroelectric memory device and method of manufacturing the same A ferroelectric memory device, which includes a vertical ferroelectric capacitor having an electrode distance smaller than a minimum feature size of lithography... |
| US-7,535,744 |
Semiconductor integrated circuit and IC card system having internal
information protection A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and... |
| US-7,535,743 |
SRAM memory cell protected against current or voltage spikes A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at... |
| US-7,535,742 |
Biasing and shielding circuit for source side sensing memory A shielding circuit for preventing a sense current of a target cell from the influence of a source current of first adjacent cell includes a pre-discharge... |
| US-7,535,741 |
Semiconductor device The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated... |
| US-7,535,740 |
Electronic apparatus and power circuit having reduced switching loss An electronic apparatus having a load including: a power supply unit supplying a driving voltage to the load; an inverter unit switching the driving voltage; and... |
| US-7,535,739 |
Semiconductor switch A semiconductor switch interrupts output when a microcomputer or an external IC operates abnormally is connected to a control device such, and is turned on or... |
| US-7,535,738 |
Method and apparatus including multi-drive configurations for medium
voltage loads A method and apparatus for converting X phase intermediate voltages on X intermediate lines to output voltage for driving a single three phase load, the... |
| US-7,535,737 |
AC/AC multiple-phase power converter configured to be mounted on a
substrate An arrangement is provided a converter, an inverter, a smoothing condenser connected between the converter and the inverter, and reactors each connected between... |
| US-7,535,736 |
Switching power supply for reducing external parts for overcurrent
protection A switching power supply has a switching device connected via a primary winding of a transformer to DC input voltage; a circuit for rectifying voltage at a... |
| US-7,535,735 |
Compensation for parameter variations in a feedback circuit Techniques to compensate for parameter variations in a feedback circuit are disclosed. In one embodiment, a regulator circuit includes an energy source coupled... |
| US-7,535,734 |
High power-factor AC/DC converter with parallel power processing The present invention is an AC/DC (alternating current to direct current) converter. The converter contains two semi-stages. One is the boost-flyback semi-stage... |
| US-7,535,733 |
Method of controlling DC-to-DC converter whereby switching control
sequence applied to switching elements... In a DC-to-DC converter which can convert DC power supplied to a first voltage system circuit, having first and second switching elements, to DC power at a... |
| US-7,535,731 |
Retention device A retention device is applied in an electronic device that has a case and a circuit board. The circuit board may shift relative to the case along a integrate... |
| US-7,535,730 |
Method of accessing a motherboard to which a daughter card is connected A method of accessing a motherboard in a computer system includes, during sliding of a card along a guide slot in the system, automatically interacting a first... |
| US-7,535,729 |
Optoelectronic system and method for its manufacture An optoelectronic system includes a printed circuit board having a ground pad and a bond pad as well as an optoelectronic element. The optoelectronic element is... |
| US-7,535,728 |
Electronic assemblies comprising ceramic/organic hybrid substrate with
embedded capacitors To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in... |
| US-7,535,727 |
Light source module A light source module includes a circuit board on which a predetermined conductive pattern is formed, a semiconductor light emitting element mounted on the... |
| US-7,535,726 |
System and method for assembling components in an electronic device The invention provides a system of components in an electronic device. The system comprises: a PCB; a first component mounted to the PCB; a cap located about the... |
| US-7,535,724 |
Printed wiring board and a method of manufacturing the same This patent specification describes a printed wiring board which includes an insulating board, a wiring pattern, and a resistor pattern. The wiring pattern... |
Copyright 2008−2012 Patents.com
