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| Patent # | Description |
|---|---|
| US-7,536,627 |
Storing downloadable firmware on bulk media A portion of data stored in a non-volatile memory may be found to be corrupted when it is read. Where parity data is generated from portions of data and parity... |
| US-7,536,626 |
Power control using erasure techniques Techniques for performing erasure detection and power control for a transmission without error detection coding are described. For erasure detection, a... |
| US-7,536,625 |
Maintaining data integrity in a data storage system A method of recovering data on a storage medium is provided. A first error correction scheme is performed on a high risk region of the storage medium. A second... |
| US-7,536,624 |
Sets of rate-compatible universal turbo codes nearly optimized over
various rates and interleaver sizes A method and apparatus for Turbo encoding uses a set of rate-compatible Turbo Codes optimized at high code rates and derived from a universal constituent code.... |
| US-7,536,623 |
Method and apparatus for generating a low-density parity check code A low density parity check (LDPC) code generating method and apparatus are provided. A parity check matrix with (N-K) rows for check nodes and N columns for... |
| US-7,536,622 |
Data repair enhancements for multicast/broadcast data distribution A method, system, device, and computer code product is disclosed in which a sender transmits data to a plurality of receivers via a point-to-multipoint session.... |
| US-7,536,621 |
Quantized data-dependent jitter injection using discrete samples Methods, system, and computer programs for compensating for introducing data dependent jitter into a test signal using a testing instrument are disclosed. The... |
| US-7,536,620 |
Method of and apparatus for validation support, computer product for
validation support An information input unit inputs functional configuration information representing a function of a device to be validated. A condition input unit inputs... |
| US-7,536,619 |
RAM testing apparatus and method Since fault detection is not conducted for the address other than the noted address or the expected value other than the noted expected value in the RAM test,... |
| US-7,536,618 |
Wide frequency range signal generator and method, and integrated circuit
test system using same A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a... |
| US-7,536,617 |
Programmable in-situ delay fault test clock generator A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and... |
| US-7,536,616 |
JTAG testing arrangement JTAG test equipment arranged to establish an asynchronous data transmission connection with a JTAG-compatible device under test for the transmission of test data... |
| US-7,536,615 |
Logic analyzer systems and methods for programmable logic devices A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among... |
| US-7,536,614 |
Built-in-redundancy analysis using RAM A method for testing memory in an integrated circuit device is disclosed. The method includes executing a test routine in a portion of the memory at a speed... |
| US-7,536,613 |
BIST address generation architecture for multi-port memories Disclosed is testing multi-port array macros where latches and logic are used to control the relationship between the write and read port of the array. This... |
| US-7,536,612 |
Field spike monitor for MRAM A method for monitoring field events in an MRAM memory device comprises providing a first magnetic storage cell having a switching threshold less than or equal... |
| US-7,536,611 |
Hard BISR scheme allowing field repair and usage of reliability controller A BISR scheme which provides for on-chip assessment of the amount of repair on a given memory and for the flagging of any device as a fail when the device... |
| US-7,536,610 |
Method for detecting resistive-open defects in semiconductor memories The present invention relates to a method for detecting delay faults in a semiconductor memory. In an example embodiment, address bits and data bits are... |
| US-7,536,609 |
Reasonable clock adjustment for storage system A system for managing clock adjustment in a storage system is provided. The system includes a clock configured to provide a current time, wherein the current... |
| US-7,536,608 |
System and method for using network interface card reset pin as indication
of lock loss of a phase locked loop... A method for providing an indication from a network interface controller to a microcontroller is disclosed wherein upon occurrence of a particular condition... |
| US-7,536,607 |
Task sequence integration and execution mechanism with automated global
condition checking and compensation A method for verifying that a sequence of tasks is more likely to be successful prior to executing the sequence of tasks. First, a projection algorithm is... |
| US-7,536,606 |
Error detection in web services systems Methods and systems are provided for automatically generating an accurate model of communications processes between disparate computing systems that may be... |
| US-7,536,605 |
Injection of software faults into an operational system A method is provided for injecting faults into an operational system containing software and hardware components to be tested. A fault injection routine is... |
| US-7,536,604 |
Method and system for reconfiguring functional capabilities in a data
processing system with dormant resources A method, a computer program product and a system for reconfiguring functional capabilities in a data processing system with dormant resources. Dormant resources... |
| US-7,536,603 |
Maintaining functionality during component failures Maintaining functionality during component failures is presented. During application registration, a recovery engine generates a recovery plan for the... |
| US-7,536,602 |
Method and apparatus for evaluating paths in a state machine Methods and apparatus are provided for exploring paths through a graph representation of a program or another entity. According to one aspect of the invention,... |
| US-7,536,601 |
Method, system and program for identifying a test specification for
testing a file element A file validator technique for identifying a test specification to be used for testing validity of a file element associated with a file is provided. The test... |
| US-7,536,600 |
Methods and apparatus for eliminating lower value tests for a unit under
test, and for developing a plurality... In one embodiment, test execution times are determined for a plurality of tests that are to be executed for a single unit under test (UUT). Test dependencies are... |
| US-7,536,599 |
Methods and systems for validating a system environment Methods, systems, and machine-readable mediums are disclosed for validating a system environment for a software application. In one embodiment, an input file... |
| US-7,536,598 |
Computer system capable of supporting a plurality of independent computing
environments A method for a computer repairing itself to an operational status at any time during operation, the method comprising the computer-executed steps of: booting... |
| US-7,536,597 |
Apparatus and method for controlling power, clock, and reset during test
and debug procedures for a plurality... An interface unit is provided for use with a JTAG test and debug procedure involving a plurality of processor cores. The interface unit is provided with a logic... |
| US-7,536,596 |
Remotely controlled channel emulator for testing of mainframe peripherals A method and a system to emulate a mainframe data channel for testing and diagnostics of mainframe peripheral devices and for remote control and configuration of... |
| US-7,536,595 |
Systems, devices, and methods for initiating recovery Certain exemplary embodiments comprise method that can comprise receiving information indicative of a fault from a monitor associated a network. The method can... |
| US-7,536,594 |
Watchdog device that provides and interrupts power to a network device in
response to a lockup error condition The invention relates to a stand-alone video recording, playback and Monitoring system. It has network switches, non-volatile storage devices, IP cameras, video... |
| US-7,536,593 |
Apparatus, system, and method for emergency backup An apparatus, system, and method quickly backs up data in an emergency situation and reduces battery backup dependence. The apparatus may include a backup module... |
| US-7,536,592 |
Storage system and snapshot data preparation method in storage system The present invention is devised so that snapshot data preparation processing does not end abnormally as a result of the pool region becoming full with saved... |
| US-7,536,591 |
Transparent checkpointing and process migration in a distributed system A distributed system for creating a checkpoint for a plurality of processes running on the distributed system. The distributed system includes a plurality of... |
| US-7,536,590 |
Programmable controller, programmable controller system, CPU unit and
method of starting duplexed operation A programmable controller has a first (executing) CPU unit and a second (standby) CPU unit for a duplexed operation. Each CPU unit stores CPU version indicating... |
| US-7,536,589 |
Processing apparatus A processing apparatus includes a plurality of operation units each of which performs a given operation for an input operand in accordance with an operating... |
| US-7,536,588 |
Method for servicing storage devices in a bladed storage subsystem A bladed storage servicing system comprising a RAID layout facilitates the removal of one or more functional storage devices in a tray of the bladed storage... |
| US-7,536,587 |
Method for the acceleration of the transmission of logging data in a
multi-computer environment and system... This invention relates to a method for the transmission of logging data, within a cluster of computers, enabling all or part of the events constituting the... |
| US-7,536,586 |
System and method for the management of failure recovery in multiple-node
shared-storage environments A storage architecture and method for managing the operation of a network in a RAID environment is provided in which a storage management agent is included in... |
| US-7,536,585 |
Method of estimating storage system availability An embodiment of a method of estimating storage system availability begins with a first step of modeling a storage system design in operation under a workload to... |
| US-7,536,584 |
Fault-isolating SAS expander A SAS expander includes SAS PHYs for transceiving signals with SAS devices on corresponding SAS links coupled to the SAS PHYs. The SAS expander includes status... |
| US-7,536,583 |
Technique for timeline compression in a data store A technique for timeline compression in a data store is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for timeline... |
| US-7,536,582 |
Fault-tolerant match-and-set locking mechanism for multiprocessor systems A match-and-set lock has a locked operating state and an unlocked operating state controlled by the value C. The lock returns a value R=C, to an inquiring user... |
| US-7,536,581 |
Automatic migratable services Singleton services can be automatically migrated from one application server to another in a cluster using a lease table and a migration master in case of a... |
| US-7,536,580 |
System and method for generating timer output corresponding to timer
request from plurality of processes The present invention relates to timer generation corresponding to a plurality of timer requests, etc. necessary for task processes of a CPU and achieves... |
| US-7,536,579 |
Skew-correcting apparatus using iterative approach An apparatus for determining the amount of skew to be injected for system skew compensation in a high-speed data communications system including a plurality of... |
| US-7,536,578 |
Method and apparatus for over clocking in a digital processing system A method of determining a maximum optimum clock frequency at which a digital processing system can operate, the method comprising the steps of: generating a... |
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