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| Patent # | Description |
|---|---|
| US-7,534,717 |
Method of manufacturing semiconductor device The formation of an interlayer insulating film above a substrate, the formation of an insulating film of an organic material on the interlayer insulating film... |
| US-7,534,716 |
System and method for venting pressure from an integrated circuit package
sealed with a lid A system and method is disclosed for venting pressure from an integrated circuit package that is sealed with a lid. During a surface mount process for mounting a... |
| US-7,534,715 |
Methods including fluxless chip attach processes Electronic devices and methods for fabricating electronic devices are described. One method includes providing a plurality of first metal bumps on a first... |
| US-7,534,714 |
Radial temperature control for lattice-mismatched epitaxy Methods are disclosed of fabricating a compound nitride semiconductor structure. A substrate is disposed over a susceptor in a processing chamber, with the... |
| US-7,534,713 |
High density chalcogenide memory cells A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a... |
| US-7,534,712 |
Semiconductor device and method for fabricating the same The semiconductor device comprises a silicon substrate 10 having a device region 11, a transistor including a gate electrode 20 formed in the device region 11... |
| US-7,534,711 |
System and method for direct etching System and method for direct etching. According to an embodiment, the present invention provides a method for manufacturing an integrated circuit device. The... |
| US-7,534,710 |
Coupled quantum well devices (CQWD) containing two or more direct
selective contacts and methods of making same The present invention relates to a device structure that contains two or more conducting layers, two peripheral insulating layers, one or more intermediate... |
| US-7,534,709 |
Semiconductor device and method of manufacturing the same Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor... |
| US-7,534,708 |
Recessed-type field effect transistor with reduced body effect For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the... |
| US-7,534,707 |
MOS Transistors having inverted T-shaped gate electrodes and fabrication
methods thereof MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in... |
| US-7,534,706 |
Recessed poly extension T-gate A method is provided for making a silicided gate in a semiconductor device. In accordance with the method, a gate (213) is provided which comprises a first... |
| US-7,534,705 |
Method of manufacturing a semiconductor device An impurity of one conductivity type is ionized and accelerated by electric field before being implanted into a semiconductor layer to form a high concentration... |
| US-7,534,704 |
Thin layer structure and method of forming the same In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing... |
| US-7,534,703 |
Method for bonding semiconductor chip A method for bonding a semiconductor chip is disclosed. In accordance with the method of the present invention, a front surface of a wafer is mounted in a wafer... |
| US-7,534,702 |
Method for manufacturing a semiconductor device An efficient mass-production method of very small devices that can receive or transmit data in touch, preferably, out of touch is provided by forming an... |
| US-7,534,701 |
Process for transferring a layer of strained semiconductor material A process for preparing a semiconductor wafer with a strained layer having an elevated critical thickness. A first wafer having a strained layer of a... |
| US-7,534,700 |
Method of fabricating a semiconductor device having a film in contact with
a debonded layer A semiconductor device in which degradation due to permeation of water and oxygen can be limited, e.g., a light emitting device having an organic light emitting... |
| US-7,534,699 |
Separating and assembling semiconductor strips A method and an apparatus for separating elongated semiconductor strips from a wafer of semiconductor material are disclosed. Vacuum is applied to the face of... |
| US-7,534,698 |
Methods of forming semiconductor devices having multilayer isolation
structures A semiconductor device includes a first structure having a recess having a bottom and opposing side surfaces, and a second structure conformally disposed on the... |
| US-7,534,696 |
Multilayer interconnect structure containing air gaps and method for
making A multilevel air-gap-containing interconnect structure and a method of fabricating the same are provided. The multilevel air-gap-containing interconnect... |
| US-7,534,695 |
Method of manufacturing a semiconductor device A semiconductor-device manufacturing method includes forming an element separating insulating film on a semiconductor substrate; forming a gate multilayer film... |
| US-7,534,694 |
Methods of forming a plurality of capacitors The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a... |
| US-7,534,693 |
Thin-film capacitor with a field modification layer and methods for
forming the same A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom... |
| US-7,534,692 |
Process for producing an integrated circuit comprising a capacitor An integrated circuit is produced to include interconnection levels each incorporating a metallization level covered with an insulating material. The integrated... |
| US-7,534,691 |
Isolation structures for preventing photons and carriers from reaching
active areas and methods of formation Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep,... |
| US-7,534,690 |
Non-volatile memory with asymmetrical doping profile Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the... |
| US-7,534,689 |
Stress enhanced MOS transistor and methods for its fabrication A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and... |
| US-7,534,688 |
Nonvolatile memory device with a non-planar gate-insulating layer and
method of fabricating the same A non-volatile memory device with a non-planar gate insulating layer and a method of fabricating the same are provided. The device includes a tunnel insulating... |
| US-7,534,687 |
Semiconductor device and method for manufacturing the same A semiconductor device, comprises: a transistor having structured to include a gate electrode formed on a semiconductor layer on a semiconductor substrate via a... |
| US-7,534,686 |
Multi-structured Si-fin and method of manufacture Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is... |
| US-7,534,685 |
Method for fabrication of a capacitor, and a monolithically integrated
circuit comprising such a capacitor A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench (14), which reaches down to the... |
| US-7,534,684 |
Methods of forming non-volatile memory devices having a multi-layered
charge storage layer A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A... |
| US-7,534,683 |
Method of making a MOS-gated transistor with reduced miller capacitance A trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then... |
| US-7,534,682 |
Semiconductor memory device with a stacked gate including a floating gate
and a control gate and method of... A semiconductor memory device includes first and second MOS transistors. The first MOS transistor is formed on a region enclosed by a first element isolating... |
| US-7,534,681 |
Memory device fabrication The invention provides methods of fabricating memory devices. One embodiment forms a bulk insulation layer overlying a plurality of source/drain regions formed... |
| US-7,534,680 |
Bipolar transistor, BiCMOS device, and method for fabricating thereof Provided are bipolar transistor, BiCMOS device and method of fabricating thereof, in which an existing sub-collector disposed beneath a collector of a SiGe HBT... |
| US-7,534,679 |
System and method for producing a semiconductor circuit arrangement Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive... |
| US-7,534,678 |
Methods of forming CMOS integrated circuit devices having stressed NMOS
and PMOS channel regions therein and... Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering... |
| US-7,534,677 |
Method of fabricating a dual gate oxide A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate,... |
| US-7,534,676 |
Method of forming enhanced device via transverse stress In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of... |
| US-7,534,675 |
Techniques for fabricating nanowire field-effect transistors Techniques for the fabrication of field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a method of fabricating a FET is provided... |
| US-7,534,674 |
Method of making a semiconductor device with a stressor First and second transistors are formed adjacent to each other. Both transistors have gate sidewall spacers removed. A stressor layer is formed overlying the... |
| US-7,534,672 |
Tiered gate device with source and drain extensions In one embodiment, a tiered gate device is provided including a source, a drain, and a gate foot therebetween. A gate head is attached to the gate foot. A source... |
| US-7,534,671 |
Method for integrally forming an electrical fuse device and a MOS
transistor A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps.... |
| US-7,534,670 |
Semiconductor device and manufacturing method of the same Provided is a technique of effectively removing a metallic element that has catalytic action in terms of the crystallization of a semiconductor film and remains... |
| US-7,534,669 |
Method and structure to create multiple device widths in FinFET technology
in both bulk and SOI Disclosed is a structure and method for producing a fin-type field effect transistor (FinFET) that has a buried oxide layer over a substrate, at least one first... |
| US-7,534,668 |
Method of fabricating etch-stopped SOI back-gate contact The buried oxide region has a layer added which etches selectively with respect to oxide, allowing the contacts to a gate or to a back gate to be created without... |
| US-7,534,667 |
Structure and method for fabrication of deep junction silicon-on-insulator
transistors A structure and method for fabricating a transistor structure is provided. The method comprises the steps of: (a) providing a substrate including a ... |
| US-7,534,666 |
High voltage non punch through IGBT for switch mode power supplies A process for forming an NPT IGBT in a thin N type silicon wafer in which the bottom surface of a thin silicon wafer (100 microns thick or less) has a shallow... |
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