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| Patent # | Description |
|---|---|
| US-7,539,078 |
Circuits to delay a signal from a memory device Various apparatus and methods include a clock circuit to receive a first clock signal to generate a second clock signal having a frequency different from a... |
| US-7,539,077 |
Flash memory device having a data buffer and programming method of the
same A flash memory device includes a memory cell array with multiple memory cells, a data buffer, a write driver and a controller. The data buffer stores data to be... |
| US-7,539,076 |
Variable data width memory systems and methods Systems and methods disclosed herein provide for variable data width memory. For example, in accordance with an embodiment of the present invention, a technique... |
| US-7,539,075 |
Implementation of a fusing scheme to allow internal voltage trimming Methods and apparatuses for adjusting trim settings for internally generated voltages of an integrated circuit device are provided. In one embodiment the... |
| US-7,539,074 |
Protection circuit with antifuse configured as semiconductor memory
redundancy circuitry A semiconductor device includes a fuse part including an antifuse that is connected between a first common node to which a high voltage that is higher than an... |
| US-7,539,073 |
Memory device with auxiliary precharge unit to improve precharge operation
for bit line circuitry A semiconductor memory device having a shared bit line sense amplifier structure is provided. The semiconductor memory device includes: a plurality of cell... |
| US-7,539,072 |
Semiconductor memory device A semiconductor memory device generates an internal voltage by using one detecting circuit at the burn-in and normal modes. The semiconductor memory device... |
| US-7,539,071 |
Semiconductor device with a relief processing portion Each of a plurality of redundant memories includes a plurality of memory cells and is operable to be relieved when a defective cell exists. This plurality of... |
| US-7,539,070 |
Semiconductor memory apparatus and method of resetting input/output lines
of the same A semiconductor memory apparatus includes a plurality of unit cell blocks formed in row and column directions, at least a pair of first input and output lines... |
| US-7,539,069 |
Semiconductor memory device This disclosure concerns a memory comprising a memory cell; a first and a second sense nodes transmitting the data on the first and the second bit lines which... |
| US-7,539,068 |
Memory and multi-state sense amplifier thereof The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled... |
| US-7,539,067 |
Semiconductor integrated circuit device A semiconductor integrated circuit device includes a data circuit and a group of bit line application voltage terminals to which different voltages are applied.... |
| US-7,539,066 |
Method, apparatus, and system for improved erase operation in flash memory Various embodiments include erasing at least one memory cell of a string of memory cells of a memory device while a control gate of at least one of a first... |
| US-7,539,065 |
Method of programming non-volatile memory A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The... |
| US-7,539,064 |
Precharge circuit of semiconductor memory apparatus A precharge circuit of a semiconductor memory apparatus includes a first precharge unit and a second precharge unit. The first precharge unit applies a first... |
| US-7,539,063 |
Flash memory devices and programming methods for the same Flash memory devices and methods of programming the same are provided. The flash memory devices include a plurality of memory cells storing multi-bit data... |
| US-7,539,062 |
Interleaved memory program and verify method, device and system An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The... |
| US-7,539,061 |
Method of programming flash memory device At the time of a program of a NAND flash memory device, a re-program is performed on a cell connected to the last word line after program and program... |
| US-7,539,060 |
Non-volatile storage using current sensing with biasing of source and
P-Well A non-volatile storage device in which current sensing is performed for a non-volatile storage element. A voltage is applied to a selected word line of the first... |
| US-7,539,059 |
Selective bit line precharging in non volatile memory A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells with strings of memory cells connected to... |
| US-7,539,058 |
Non-volatile memory and operating method thereof A non-volatile memory and an operating method thereof. The non-volatile memory includes a memory cell array, a first dummy cell array, an address decoding unit... |
| US-7,539,057 |
Erase and program method of flash memory device for increasing program
speed of flash memory device Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so... |
| US-7,539,056 |
Nonvolatile semiconductor memory In a NAND type flash memory, control electrodes of first select transistors in a plurality memory cell units extending along a data line is integrated to... |
| US-7,539,055 |
Non-volatile semiconductor memory and method for controlling a
non-volatile semiconductor memory A non-volatile semiconductor memory includes a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region... |
| US-7,539,054 |
Method and apparatus to program and erase a non-volatile static random
access memory from the bit lines A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile... |
| US-7,539,053 |
Non-volatile semiconductor memory device A non-volatile semiconductor memory device includes plurality of word lines and a plurality of bit lines comprising even numbered bit lines and odd numbered bit... |
| US-7,539,052 |
Non-volatile multilevel memory cell programming Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number... |
| US-7,539,051 |
Memory storage devices comprising different ferromagnetic material layers,
and methods of making and using the same A memory storage device that contains alternating first and second ferromagnetic material layers is provided. Each first ferromagnetic material layer has a first... |
| US-7,539,050 |
Resistive memory including refresh operation A memory device includes an array of resistive memory cells, a counter having an increment step based on temperature, and a circuit for refreshing the memory... |
| US-7,539,049 |
Magnetic random access memory and operation method A magnetic random access memory includes at least a first-direction write current line and multiple second-direction write current line, intersecting with the... |
| US-7,539,048 |
Method and apparatus processing variable resistance memory cell write
operation A circuit and method for writing to a variable resistance memory cell. The circuit includes a variable resistance memory cell, a switchable current blocking... |
| US-7,539,047 |
MRAM cell with multiple storage elements An improved MRAM cell may include a first, second, and third contact, a first MTJ between the first and second contact, and a MTJ between the second and third... |
| US-7,539,046 |
Integrated circuit with magnetic memory An integrated circuit with magnetic memory has a silicon transistor layer, at least one magnetic memory layer, and a metal routing layer. The silicon transistor... |
| US-7,539,045 |
Method and device for improved magnetic field generation during a write
operation of a magnetoresistive memory... Magnetic or magnetoresistive random access memories (MRAMs) are implemented in a variety of arrangements and methods. Using one such arrangement, a matrix is... |
| US-7,539,044 |
Memory device with capacitor and diode One embodiment of the present invention relates to an integrated circuit that includes a memory cell. The memory cell includes a capacitor configured to store a... |
| US-7,539,043 |
Semiconductor memory device This disclosure concerns a memory comprising a memory cell including a floating body provided between a source and a drain and storing therein data according to... |
| US-7,539,042 |
Semiconductor device and fabrication method thereof The present invention suppresses the refresh failure of a DRAM due to the dispersion of a threshold of a MOSFET. The DRAM has a first unit for recording a set... |
| US-7,539,041 |
Floating body semiconductor memory device and method of operating the same A semiconductor memory device includes a memory cell array having first and second blocks, respectively including first and second memory cells with floating... |
| US-7,539,040 |
Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device comprises a memory cell including a variable resistance element changing its electric resistance by voltage application... |
| US-7,539,039 |
Integrated circuit having a resistive switching device An integrated circuit, a memory cell, memory device and method of operating the memory device is disclosed. In one embodiment, an integrated circuit having a... |
| US-7,539,038 |
Nonvolatile nanochannel memory device using organic-inorganic complex
mesoporous material A memory device of the current invention includes a memory layer having nanochannels sandwiched between an upper electrode and a lower electrode, in which the... |
| US-7,539,036 |
Semiconductor memory device including plurality of memory mats A semiconductor memory device includes a plurality of memory mats each including a memory cell storing data, a sense latch portion performing detection of data... |
| US-7,539,035 |
Memory system capable of changing configuration of memory modules A memory system is disclosed with first, second, and third connectors located on a system board, the third connector including pins connected to the pins of the... |
| US-7,539,034 |
Memory configured on a common substrate A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and... |
| US-7,539,033 |
Semiconductor memory device There is provided a semiconductor memory device which offers enhanced speed in burst mode. The semiconductor memory device has a burst mode for serially reading... |
| US-7,539,032 |
Regular expression searching of packet contents using dedicated search
circuits A network system includes a content search system for determining whether an input string matches a regular expression comprising an exact pattern and an inexact... |
| US-7,539,031 |
Inexact pattern searching using bitmap contained in a bitcheck command A search circuit for determining whether an input string including a plurality of input characters matches an inexact pattern including a number of pattern... |
| US-7,539,030 |
Attribute cache memory A memory system according to one embodiment includes a plurality of content addressable word decoders, and memory cells associated with each of the word... |
| US-7,539,029 |
3-phase solar converter circuit and method A conversion circuit for converting solar power into an alternating 3-phase mains comprises a converter for converting the power from a solar cell into an... |
| US-7,539,028 |
Method and apparatus for fault detection in a switching power supply Techniques are disclosed to detect a fault in the feedback circuit of a switching power supply while the power supply operates in a mode where the output is... |
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