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| Patent # | Description |
|---|---|
| US-7,539,932 |
Method and system for debugging Ethernet A system is disclosed and claimed for debugging Ethernet adapters and Ethernet adapter device drivers by automatically monitoring Ethernet adapter functionality... |
| US-7,539,931 |
Storage element for mitigating soft errors in logic In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock... |
| US-7,539,930 |
System, method and apparatus of protecting a wireless transmission Embodiments of the present invention provide a method, apparatus and system of protecting a wireless transmission. The method according to some demonstrative... |
| US-7,539,929 |
Error correction for data communication Generating a check matrix includes defining a generator function operable to yield check bits associated with a word. A set of primitive elements is calculated... |
| US-7,539,928 |
Method and apparatus for decoding inner and outer codes in a mobile
communication system A method and apparatus for decoding inner and/or outer codes in a mobile communication system. The inner and/or outer codes are decoded at low power and high... |
| US-7,539,927 |
High speed hardware implementation of modified Reed-Solomon decoder A decoder suitable for use in a digital communications system utilizing an RS(n', k') code modified from an RS(n, k) code receives n'-symbol vectors each... |
| US-7,539,926 |
Method of correcting errors stored in a memory array A method of correcting errors stored in a memory array is disclosed. According to various embodiments of the invention, the method comprises the steps of storing... |
| US-7,539,925 |
Transmission apparatus and method, reception apparatus and method, storage
medium, and program A congestion/non-congestion determining unit determines whether or not a communications network is in a congestion state. An FEC (forward error correction)... |
| US-7,539,924 |
Disk drive implementing data path protection by encoding large host blocks
into sub blocks A disk drive is disclosed including a disk having a plurality of data tracks, wherein each data track includes a plurality of data sectors. A head is actuated... |
| US-7,539,923 |
Circuit and method of transmitting a block of data A circuit for transmitting a block of data is disclosed. The circuit comprises a memory array having a plurality of memory locations coupled to receive data; a... |
| US-7,539,922 |
Bit failure detection circuits for testing integrated circuit memories A bit failure detection circuit supports reliability testing of a memory device by accumulating a sum of data errors in data read from the memory device. The... |
| US-7,539,921 |
Parity bit system for a CAM A CAM includes a parity bit system for error detection. In one embodiment, in each CAM cell, the data portion has its own data parity bit while the status... |
| US-7,539,920 |
LDPC decoding apparatus and method with low computational complexity
algorithm Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative... |
| US-7,539,919 |
Optical recording medium, apparatus and method of recording/reproducing
data thereon/therefrom, and... A recording medium on which a recording/reproducing unit block is recorded, an apparatus to record and/or reproduce data on/from the recording medium, and a... |
| US-7,539,918 |
System and method for generating cyclic codes for error control in digital
communications A K-bit information signal represented by a polynomial U(x) having a degree K-1 is received. The information signal is transformed to form a transformed... |
| US-7,539,917 |
Acknowledgement signaling for automatic repeat request mechanisms in
wireless networks The present invention purposes an enhanced acknowledgment/non-acknowledgment signaling applicable to automatic repeat request mechanisms. The automatic repeat... |
| US-7,539,916 |
BIST to provide phase interpolator data and associated methods of
operation In an embodiment, a phase interpolator (PI) circuit is in an integrated circuit with a test latch, and the test latch is enabled by a test clock signal to... |
| US-7,539,915 |
Integrated circuit testing using segmented scan chains An integrated circuit, and associated method and computer program, comprises a first scan chain portion comprising a plurality of first storage elements to... |
| US-7,539,914 |
Method of refreshing configuration data in an integrated circuit Configuration memory cells in an integrated circuit (IC) may be corrupted by cosmic radiation and other sources, causing improper operation of the IC.... |
| US-7,539,913 |
Systems and methods for chip testing Circuit and method for testing digital logic circuit modules of an integrated circuit chip. The circuit includes a storage device, a first multiplexing module... |
| US-7,539,912 |
Method and apparatus for testing a fully buffered memory module Described embodiments relate to a method of testing fully buffered memory modules that involves placing a buffer device, a test vectors generator, and a switch... |
| US-7,539,911 |
Test mode for programming rate and precharge time for DRAM
activate-precharge cycle A programmable activate-precharge cycle are provided for a DRAM device. Activate and precharge signals associated with the activate-precharge cycle are generated... |
| US-7,539,910 |
Memory module test system for memory module including hub A memory module test system including at least one memory module. The at least one memory module includes a first hub and a plurality of semiconductor memory... |
| US-7,539,909 |
Distributed memory initialization and test methods and apparatus A memory system includes multiple memory modules, which communicate with a memory controller over one or more channels. When a memory module receives an... |
| US-7,539,908 |
Apparatus having function of checking error in copying or moving file and
method thereof An apparatus having a function of checking an error in copying or moving a file and a method thereof are disclosed. The apparatus includes: a first storing unit... |
| US-7,539,907 |
Method and apparatus for determining a predicted failure rate A method and apparatus for determining predicted failure rates for computational resources provided by a system comprising multiple components. The method... |
| US-7,539,906 |
System for integrated data integrity verification and method thereof In accordance with one technique, a first plurality of values associated with data transfers between a processor and a memory is received at the processor and at... |
| US-7,539,905 |
Method of and apparatus for detecting an error in writing to persistent
memory A technique is provided for detecting errors in persistent memory, such as flash memory, where values of data items are stored at memory locations added... |
| US-7,539,904 |
Quantitative measurement of the autonomic capabilities of computing
systems The present invention is directed to the quantitative measurement of the autonomic capabilities of computing systems. A method in accordance with an embodiment... |
| US-7,539,903 |
Method for monitoring the execution of a program by comparing a request
with a response and introducing a... The invention relates to a method for monitoring the execution of a program in a microcomputer of an electronic device, especially a sensor circuit for motor... |
| US-7,539,902 |
Application level testing of instruction caches in
multi-processor/multi-core systems A method and apparatus performs computer application level testing of an instruction cache in multi-processor or multi-core systems. Instruction cache cannot be... |
| US-7,539,901 |
Data transmission management system, a mobile device and a server used
therein A data transmission control system includes a server configured to store an application program having a data area in which transmission control information... |
| US-7,539,900 |
Embedded microprocessor for integrated circuit testing and debugging A technique for embedding a microprocessor into an integrated circuit allows on-chip testing and debugging. The microprocessor present on the chip tests and... |
| US-7,539,899 |
Cloning machine and method of computer disaster recovery A computer cloning system and process comprising a cloning machine which modifies a survived or reproduced operating system ("OS") devices to adapt to new... |
| US-7,539,898 |
Method of increasing system availability by assigning process pairs to
processor pairs A method is provided of assigning processors in a multiprocessor environment to a plurality of processes that are executed in the multiprocessor environment.... |
| US-7,539,897 |
Fault tolerant system and controller, access control method, and control
program used in the fault tolerant system The present invention has been made to realize access processing performed in accordance with synchronous/asynchronous state between processors in a fault... |
| US-7,539,896 |
Repairable block redundancy scheme A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when... |
| US-7,539,895 |
Method to transfer information between data storage devices A method is disclosed to transfer information between data storage devices. The method provides an information storage assembly comprising a frame, a memory... |
| US-7,539,894 |
Method for accessing data of defected optical disk A method for accessing data in an optical disk with a drive. The drive has a memory. The optical disk has data blocks for recording data, and spare blocks for... |
| US-7,539,893 |
Systems and methods for speed binning of integrated circuits Methods and apparatus sort integrated circuits by maximum operating speed (f.sub.max). The timing for a first set of critical timing paths is statistically... |
| US-7,539,892 |
Enhanced resynchronization in a storage-based mirroring system having
different storage geometries Resynchronization of data between a primary (production) data site and a secondary (recovery) site following a failure is enhanced when the size of a data track... |
| US-7,539,891 |
Switched FC-AL fault tolerant topology A computer system uses a Fiber Channel Arbitrated Loop (FC-AL) network to communicate with mass storage devices. The FC-AL network provides alternative... |
| US-7,539,890 |
Hybrid computer security clock A clock object is provides, which includes a clock time and a monotonic time that are readable by the electronic device. The monotonic time is incremented every... |
| US-7,539,889 |
Media data synchronization in a wireless network A method of keeping global time in a wireless network, the method comprising the steps of: using a first 802.11 chip set to read a Time Synchronization Function... |
| US-7,539,888 |
Message buffer for a receiver apparatus on a communications bus A Controller Area Network (CAN) node consists of a high-powered microcontroller, a low standby power regulator, a CAN bus transceiver, and a minimal CAN message... |
| US-7,539,887 |
Physical layer device and power-saving method for physical layer device A method for saving electrical power for a physical layer (PHY) device including a plurality of sub-circuits is disclosed. The method includes the steps of... |
| US-7,539,886 |
Image processing apparatus, power saving control method, and program and
storage medium thereof An object is to provide an image processing apparatus which can reduce power consumption during the power saving standby mode. The starting factor monitor unit... |
| US-7,539,885 |
Method and apparatus for adaptive CPU power management A method and apparatus are disclosed for performing adaptive run-time power management in a system employing a CPU and an operating system. A CPU cycle tracker... |
| US-7,539,884 |
Power-gating instruction scheduling for power leakage reduction A method of power-gating instruction scheduling for leakage power reduction comprises receiving a program, generating a control-flow graph dividing the program... |
| US-7,539,883 |
Information processing apparatus and control method for transitioning a
state of a communication path between... According to one embodiment, an information processing apparatus includes first and second devices that are interconnected via a communication path, each of the... |
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