Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,538,019 |
Forming compliant contact pads for semiconductor packages In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second... |
| US-7,538,018 |
Gate structure and method for fabricating the same, and method for
fabricating memory and CMOS transistor layout A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate.... |
| US-7,538,017 |
Method of manufacturing a thin film transistor, a thin film transistor
manufactured by the method, a method of... Provided are a method of manufacturing a plastic substrate having a TFT, a substrate manufactured thereby, a method of manufacturing a flat panel display device,... |
| US-7,538,016 |
Signal and/or ground planes with double buried insulator layers and
fabrication process The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a... |
| US-7,538,015 |
Method of manufacturing micro structure, and method of manufacturing mold
material Disclosed herein are a method of producing microstructure and a method of producing mold, the methods permitting production of much smaller pores than before in... |
| US-7,538,014 |
Method of producing crystalline semiconductor material and method of
fabricating semiconductor device Disclosed are a method of producing a crystalline semiconductor material capable of improving the crystallinity and a method of fabricating a semiconductor... |
| US-7,538,013 |
Method of manufacturing a field effect transistor comprising an insulating
film including metal oxide having... There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a... |
| US-7,538,012 |
Fluorine-containing carbon film forming method The present invention is made to solve a problem to improve adhesion between a fluorine-containing carbon film and a foundation film. In order to achieve this... |
| US-7,538,011 |
Method of manufacturing a semiconductor device An object is to reduce the number of high temperature (equal to or greater than 600.degree. C.) heat treatment process steps and achieve lower temperature (equal... |
| US-7,538,010 |
Method of fabricating an epitaxially grown layer A method of forming an epitaxially grown layer by providing a support substrate that includes a region of weakness therein to define a support portion and a... |
| US-7,538,009 |
Method for fabricating STI gap fill oxide layer in semiconductor devices A method for fabricating an STI gap fill oxide layer in a semiconductor device is provided. The method can include: forming a shallow trench for forming an STI... |
| US-7,538,008 |
Method for producing a layer structure A layer structure comprising a smoothed interlayer and an overlying layer applied on the interlayer, wherein the interlayer is treated with a gaseous etchant... |
| US-7,538,007 |
Semiconductor device with flowable insulation layer formed on capacitor
and method for fabricating the same Disclosed is a semiconductor device with a flowable insulation layer formed on a capacitor and a method for fabricating the same. Particularly, the semiconductor... |
| US-7,538,006 |
Annular damascene vertical natural capacitor A method for forming a vertical natural capacitor in an integrated circuit is disclosed. In one embodiment, the method includes forming a first set of concentric... |
| US-7,538,005 |
Semiconductor device and method for fabricating the same A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the... |
| US-7,538,004 |
Method of fabrication for SiGe heterojunction bipolar transistor (HBT) A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on... |
| US-7,538,003 |
Method for fabricating MOS transistor A method for fabricating a metal oxide semiconductor (MOS) transistor comprises forming a source region of a first conductivity type and a drain region of the... |
| US-7,538,002 |
Semiconductor process integrating source/drain stressors and interlevel
dielectric layer stressors A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the... |
| US-7,538,001 |
Transistor gate forming methods and integrated circuits A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal... |
| US-7,538,000 |
Method of forming double gate transistors having varying gate dielectric
thicknesses Double gate transistors (12, 13) having different bottom gate dielectric thicknesses are formed on a first wafer (101) by forming a first gate dielectric layer... |
| US-7,537,999 |
Method for manufacturing a CMOS image sensor A method for manufacturing structures of a CMOS image sensor. The method comprises the steps of depositing a gate insulating layer and a conductive layer on a... |
| US-7,537,998 |
Method for forming salicide in semiconductor device Forming salicide in a semiconductor device includes the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide... |
| US-7,537,997 |
Ensuring migratability of circuits by masking portions of the circuits
while improving performance of other... Mechanisms for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency... |
| US-7,537,996 |
Self-aligned method of forming a semiconductor memory array of floating
gate memory cells with buried source... A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a... |
| US-7,537,995 |
Method for fabricating a dual poly gate in semiconductor device A method for fabricating a dual poly gate in a semiconductor device is disclosed. The method comprises forming a gate insulating layer over a semiconductor... |
| US-7,537,994 |
Methods of forming semiconductor devices, assemblies and constructions Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another... |
| US-7,537,993 |
Methods of forming semiconductor devices having tunnel and gate insulating
layers A semiconductor device includes a semiconductor substrate having a surface, buried isolation regions protruding from the surface of the semiconductor substrate,... |
| US-7,537,992 |
Method for manufacturing flash memory device A flash memory device incorporating: a semiconductor substrate having an active region and a field region defined therein; a device isolation layer formed in the... |
| US-7,537,991 |
Salicided MOS device and one-sided salicided MOS device, and simultaneous
fabrication method thereof A method of fabricating a salicided MOS and a one-sided salicided MOS device on a semiconductor substrate. A conformal oxide layer and an organic layer are... |
| US-7,537,990 |
Method of manufacturing semiconductor devices A method of manufacturing semiconductor devices includes: preparing a semiconductor substrate over which a laminated structure including an insulating layer is... |
| US-7,537,989 |
Method for manufacturing SOI substrate To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an... |
| US-7,537,988 |
Differential offset spacer A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a... |
| US-7,537,987 |
Semiconductor device manufacturing method In a semiconductor device manufacturing method of the invention, a metal film, for forming a gate electrode, is formed on a gate insulating film. Subsequently,... |
| US-7,537,986 |
Semiconductor device and method for manufacturing the same A semiconductor device comprises an active region formed in a semiconductor substrate; a recess region being formed within the active region and defining a... |
| US-7,537,985 |
Double gate isolation A double-gated fin-type field effect transistor (FinFET) structure has electrically isolated gates. In a method for manufacturing the FinFET structure, a fin,... |
| US-7,537,984 |
III-V power field effect transistors A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of... |
| US-7,537,983 |
MOSFET In various aspects, a MOSFET may include an active region of a first conductivity type provided on an insulating layer, the active region having a first portion... |
| US-7,537,982 |
Method and structure for isolating substrate noise An integrated circuit structure for isolating substrate noise and a method of forming the same are provided. In the preferred embodiment of the present... |
| US-7,537,981 |
Silicon on insulator device and method of manufacturing the same An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device... |
| US-7,537,980 |
Method of manufacturing a stacked semiconductor device In a method of manufacturing a stacked semiconductor device, a seed layer including impurity regions may be prepared. A first insulation interlayer pattern... |
| US-7,537,979 |
Method of manufacturing semiconductor device Since sodium contained in glass, or glass itself has low heat resistance; a CPU fabricated using a TFT formed over a glass substrate or the like has not been... |
| US-7,537,978 |
Semiconductor device and manufacturing method thereof A semiconductor device comprises a support layer made of semiconductor, a diffusion layer formed by implanting impurities in a surface layer of the support... |
| US-7,537,977 |
Method for manufacturing a thin film transistor array panel for a liquid
crystal display and a photolithography... A thin film transistor (TFT) array panel that includes a substrate, a gate wire formed on the substrate, a gate insulating layer pattern formed on the gate wire,... |
| US-7,537,976 |
Manufacturing method of thin film transistor The invention provides a manufacturing method of a circular thin film transistor of which shape is more controlled than the conventional case, while simplifying... |
| US-7,537,975 |
Organic thin film transistor and method of fabricating the same An organic thin film transistor (TFT) and a method of fabricating the same are provided. In the method, an organic semiconductor layer is formed by mixing carbon... |
| US-7,537,974 |
Photoresist composition, method for forming film pattern using the same,
and method for manufacturing thin film... A photoresist composition includes a novolac resin having ##STR00001## where each of R.sub.1, R.sub.2, R.sub.3, and R.sub.4 is an alkyl group having a hydrogen... |
| US-7,537,973 |
Method for fabricating structure of thin film transistor array A substrate having a gate electrode layer, a gate insulating layer, and a silicon layer thereon is provided. These layers are patterned into a gate area, a gate... |
| US-7,537,972 |
Semiconductor device and method of manufacturing the same The present invention provides the structure and manufacturing method of a semiconductor device that consumes small power even when a screen is made to be... |
| US-7,537,971 |
Method for fabricating CMOS image sensor A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor includes performing an ion implantation process onto a photodiode region... |
| US-7,537,970 |
Bi-directional transistor with by-pass path and method therefor In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have... |
Copyright 2008−2012 Patents.com
