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| Patent # | Description |
|---|---|
| US-7,545,690 |
Method for evaluating memory cell performance A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a... |
| US-7,545,689 |
Method and apparatus for improving yield in semiconductor devices by
guaranteeing health of redundancy information A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells... |
| US-7,545,688 |
Semiconductor device There is provided a semiconductor device including: plural macros each having plural normal blocks and a redundant block to be used as a replacement for a normal... |
| US-7,545,687 |
Semiconductor memory device A semiconductor memory device checks a RAS timing to recognize and set an operation timing of the semiconductor memory device. The semiconductor memory device... |
| US-7,545,686 |
Device for setting up a write current in an MRAM type memory and memory
comprising The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a... |
| US-7,545,685 |
High voltage switch circuit having boosting circuit and flash memory
device including the same A high-voltage switch circuit includes an enable control circuit, a feedback circuit, a boosting circuit, and a high voltage switch. The enable control circuit... |
| US-7,545,684 |
Nonvolatile semiconductor storage device and operation method thereof A nonvolatile semiconductor memory device includes a plurality of electronically reprogrammable memory cells, a circuit for applying a plurality of pulse signals... |
| US-7,545,683 |
Semiconductor memory device A semiconductor memory device arranged for minimizing the duration of time required for conducting a batch verify action and thus speeding up a buffer write... |
| US-7,545,682 |
Erase block data splitting A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data... |
| US-7,545,681 |
Segmented bitscan for verification of programming A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more... |
| US-7,545,680 |
Flash memory device and word line enable method thereof In one aspect, a word line enable method in a flash memory device includes driving a signal line corresponding to a selected word line with a word line voltage,... |
| US-7,545,679 |
Electrical erasable programmable memory transconductance testing A test method determines if an array of a Flash EEPROM circuit has a bit cell with a transconductance (gm) that is deficient. The method preconditions all bit... |
| US-7,545,678 |
Non-volatile storage with source bias all bit line sensing A NAND string in which bit line-to-bit line noise is discharged prior to sensing a programming condition of a selected non-volatile storage element in the NAND... |
| US-7,545,677 |
Nonvolatile memory device and methods of programming and reading the same A read method of a non-volatile memory device includes reading an initial threshold voltage value of an index cell from threshold voltage information cells that... |
| US-7,545,676 |
Well bias circuit in a memory device and method of operating the same A well bias circuit in a memory device includes a well voltage supplying circuit configured to apply a high voltage to a well for erasing data in a memory cell.... |
| US-7,545,675 |
Reading non-volatile storage with efficient setup A process for reading data (including verifying during programming) from a selected non-volatile storage elements of a group (e.g., NAND string) of non-volatile... |
| US-7,545,674 |
Flash memory with low tunnel barrier interpoly insulators Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region... |
| US-7,545,673 |
Using MLC flash as SLC by writing dummy data A method for storing data includes designating, in a memory array including cells configured for writing a first number of bits per cell, a group of the cells to... |
| US-7,545,672 |
Spin injection write type magnetic memory device A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The... |
| US-7,545,671 |
Static random access memory cell with improved stability A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a... |
| US-7,545,670 |
Dual word line or floating bit line low power SRAM Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a... |
| US-7,545,669 |
Resistive memory device A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal,... |
| US-7,545,668 |
Mushroom phase change memory having a multilayer electrode An integrated circuit includes a first electrode including at least two electrode material layers and a resistivity changing material including a first portion... |
| US-7,545,667 |
Programmable via structure for three dimensional integration technology A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change... |
| US-7,545,666 |
Electrical fuse self test and repair A circuit for testing and repairing a fuse device having a plurality of fuse units and being able to serially input and output data is disclosed, the circuit... |
| US-7,545,665 |
High yielding, voltage, temperature, and process insensitive lateral poly
fuse memory The present invention, generally speaking, provides for a non volatile memory cell requiring no extra process steps. In one embodiment, the non volatile memory... |
| US-7,545,664 |
Memory system having self timed daisy chained memory chips A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is... |
| US-7,545,663 |
Semiconductor storage device Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality... |
| US-7,545,662 |
Method and system for magnetic shielding in semiconductor integrated
circuit A circuit with an inter-module radiation interference shielding mechanism is disclosed. The circuit includes a circuit module producing a radiation field. At... |
| US-7,545,661 |
Content addressable memory with twisted data lines A content addressable memory (CAM) device having CAM cells arranged in rows and columns. A plurality of pairs of data lines extend along respective columns of... |
| US-7,545,660 |
Method and apparatus for CAM with reduced cross-coupling interference A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed. |
| US-7,545,659 |
Method and apparatus for cycle error correction for a power converter
device, such as an electronic power inverter Cycle error correction is performed in an electronic power system to compensate for a difference between an AC grid side frequency and an AC load side frequency.... |
| US-7,545,658 |
DC-DC boost converter with a charge pump A DC-DC boost converter comprises a charge pump selectively operating in a voltage doubler or in a voltage tripler mode. A switching arrangement connects the... |
| US-7,545,657 |
Switching power source apparatus A switching power source apparatus includes a switching element connected through a primary winding of a transformer to a DC power source, a start circuit for a... |
| US-7,545,656 |
Common mode noise reduction circuit utilizing dual primary windings A common mode noise cancellation circuit eliminates common mode noise generated by a high-frequency switching device. The common mode noise reduction circuit... |
| US-7,545,655 |
Inverter apparatus An inverter apparatus in which a control power source connected to a microcomputer or a peripheral circuit included in at least one of an inverter main body, a... |
| US-7,545,654 |
Control circuit for current and voltage control in a switching power
supply A control circuit and method for controlling the output voltage and/or the output current of a switching power supply. The control circuit includes a transformer... |
| US-7,545,653 |
Semiconductor integrated circuit device A disclosed semiconductor integrated circuit device includes a digital circuit and an analog circuit formed on one semiconductor substrate; a guard band... |
| US-7,545,652 |
Printed circuit board and differential signaling structure Provided is a system adopting a differential signaling system including a low frequency signaling line arranged to be adjacent to a pair of differential... |
| US-7,545,651 |
Memory module with a predetermined arrangement of pins A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a... |
| US-7,545,650 |
Systems for retaining expansion cards An apparatus comprising a chassis defining an attachment slot suitable for receiving a first end of an expansion card and a bracket coupled to the chassis, the... |
| US-7,545,649 |
Double sided flexible printed circuit board A flexible printed circuit board includes a flexible substrate having a first region, a second region and a third region; a first conductive foil layer disposed... |
| US-7,545,648 |
Cooling structure using rigid movable elements An information processing system includes: a processor; a memory; an input/output subsystem; and a bus coupled to the processor, the memory and the input/output... |
| US-7,545,647 |
Compliant thermal interface structure utilizing spring elements A structure for cooling an electronic device is disclosed. The structure includes a solid heat-conducting layer disposed over the electronic device. The solid... |
| US-7,545,646 |
Cooling assembly A cooling assembly and method of cooling a heat-generating electronic component on a circuit board. A heat collector collects heat from the electronic component.... |
| US-7,545,645 |
Heat dissipation device A heat dissipation device includes a heat spreader (20), a heat pipe (30), a heat sink (40) and a cooling fan (50) for generating forced airflow to the heat... |
| US-7,545,644 |
Nano-patch thermal management devices, methods, & systems Nano-scale thermal management devices, methods, and systems are provided. According to some embodiments, a thermal management device configured to remove heat... |
| US-7,545,643 |
Heat dissipation device with a fan duct A heat dissipation device adapted for cooling a heat-generating electronic component includes a heat sink (30), a fan (40) mounted on the heat sink (30), a fan... |
| US-7,545,642 |
Automotive dynamoelectric machine A large number of ventilating apertures that have a circular cross section are disposed through the heatsink so as to extend from an air intake apertured surface... |
| US-7,545,641 |
Computer housing shock absorber device for a vibration source frame A computer housing shock absorber device for a vibration source frame, which includes: a computer housing provided with a U-shaped holding space; an inner... |
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