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| Patent # | Description |
|---|---|
| US-7,544,632 |
Bulk Ni-Mo-W catalysts made from precursors containing an organic agent Novel bulk tri-metallic catalysts for use in the hydroprocessing of hydrocarbon feeds, as well as a method for preparing such catalysts. The catalysts are... |
| US-7,544,631 |
C and N-doped titaniumoxide-based photocatalytic and self-cleaning thin
films and the process for production... The present invention provides for titanium oxide-based photocatalysts having a general formula of TiO.sub.2-X-.delta.C.sub.XN.sub..delta. and self-cleaning... |
| US-7,544,630 |
Methods of manufacturing electrodes for polymer electrolyte fuel cells Methods are provided for easily obtaining a high performance electrode without using an organic solvent for making an ink of an electrode catalyst or a... |
| US-7,544,629 |
Non-lead glass for forming dielectric, glass ceramic composition for
forming dielectric, dielectric, and... A non-lead glass for forming a dielectric, which consists essentially of, as represented by mol %, from 20 to 39% of SiO.sub.2, from 5 to 35% of B.sub.2O.sub.3,... |
| US-7,544,628 |
Loop-forming nonwoven material for a mechanical closure element A loop-forming nonwoven material (28) is used as a mechanical closure element, in particular for disposable sanitary articles (2) such as various types of... |
| US-7,544,627 |
Pressure sensing fabric Existing pressure sensing fabrics may involve two portions, i.e., insulating and conductive portions in the fabric, which increases the complexity of the fabric... |
| US-7,544,626 |
Preparation of self-assembled silicon nanotubes by hydrothermal method The present invention relates to a method for preparing self-assembled silicon nanotubes (SiNTs) by a hydrothermal method. A method for preparing self-assembled... |
| US-7,544,625 |
Silicon oxide thin-films with embedded nanocrystalline silicon A method is provided for forming a silicon oxide (SiOx) thin-film with embedded nanocrystalline silicon (Si). The method deposits SiOx, where x is in the range... |
| US-7,544,624 |
Systems and methods for processing microfeature workpieces Systems and methods for processing microfeature workpieces are disclosed herein. In one embodiment, the system comprises a processing chamber having a workpiece... |
| US-7,544,623 |
Method for fabricating a contact hole A method for fabricating a contact hole is provided. A semiconductor substrate having thereon a conductive region is prepared. A dielectric layer is deposited on... |
| US-7,544,622 |
Passivation for cleaning a material A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove... |
| US-7,544,621 |
Method of removing a metal silicide layer on a gate electrode in a
semiconductor manufacturing process and... A method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal... |
| US-7,544,620 |
Process for digging a deep trench in a semiconductor body and
semiconductor body so obtained A process for digging deep trenches in a body of semiconductor material includes forming a mask having an opening, above a surface of a semiconductor body. A... |
| US-7,544,619 |
Method of fabricating semiconductor device An insulating film is formed on a main surface of a substrate. A conductive film is formed on the insulating film. A lower layer resist film, an intermediate... |
| US-7,544,618 |
Two-step chemical mechanical polishing process A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the... |
| US-7,544,617 |
Die scale control of chemical mechanical polishing A method for control of chemical mechanical polishing of a pattern dependant non-uniform wafer surfaces in a die scale wherein the die in the wafer surface have... |
| US-7,544,616 |
Methods of forming nitride read only memory and word lines thereof A method of forming word lines of a memory includes providing a substrate and forming a conductive layer on the substrate. A metal silicide layer is formed on... |
| US-7,544,615 |
Systems and methods of forming refractory metal nitride layers using
organic amines A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on... |
| US-7,544,614 |
Method of forming a coated film, method of forming an electronic device,
and method of manufacturing an... A slit forming process with respect to a coated film, includes: forming a step pattern having an end part on a substrate; coating a liquid material for forming... |
| US-7,544,613 |
Method of manufacturing semiconductor device with an improved wiring layer
structure A method of manufacturing a semiconductor device including word lines of memory cells and a pair of select gate lines. A first insulating film, a first... |
| US-7,544,612 |
Method and structure for reducing the effect of vertical steps in
patterned layers in semiconductor structures According to an exemplary embodiment, a method for fabricating a multilayer semiconductor structure includes forming first and second patterned segments, where a... |
| US-7,544,611 |
Method of manufacturing III-V nitride semiconductor device An aluminum gallium nitride/gallium nitride layer (III-V nitride semiconductor layer) is formed on the surface of a silicone carbide substrate. The aluminum... |
| US-7,544,610 |
Method and process for forming a self-aligned silicide contact The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a... |
| US-7,544,609 |
Method for integrating liner formation in back end of line processing A method for integrating cap liner formation in back-end-of-line (BEOL) processing of a semiconductor device includes forming a trench structure within an... |
| US-7,544,608 |
Porous and dense hybrid interconnect structure and method of manufacture A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance... |
| US-7,544,607 |
Semiconductor device having thin film formed by atomic layer deposition
and method for fabricating the same A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a... |
| US-7,544,606 |
Method to implement stress free polishing A method of forming a metal feature in a low-k dielectric layer is provided. The method includes forming an opening in a low-k dielectric layer, forming a metal... |
| US-7,544,605 |
Method of making a contact on a backside of a die A method of forming a semiconductor device includes forming active circuitry over a semiconductor substrate, wherein the semiconductor substrate has a first... |
| US-7,544,604 |
Tantalum lanthanide oxynitride films Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of... |
| US-7,544,603 |
Method of fabricating silicon nitride layer and method of fabricating
semiconductor device A method of fabricating a silicon nitride layer is described. First, a substrate is provided. Then, a silicon nitride layer is formed on the substrate. The... |
| US-7,544,602 |
Method and structure for ultra narrow crack stop for multilevel
semiconductor device An integrated circuit design and a method of fabrication and, more particularly, a semiconductor structure having an ultra narrow crack stop for use in... |
| US-7,544,601 |
Semiconductor device and a method for manufacturing the same Disclosed are embodiments relating to a semiconductor device and a method of manufacturing a semiconductor device that may prevent an increase of a dielectric... |
| US-7,544,600 |
Bumping process and bump structure A bumping process comprises forming a passivation layer having a planarized surface covering a pad on a substrate, forming a hole penetrating through the... |
| US-7,544,599 |
Manufacturing method of solder ball disposing surface structure of package
substrate A manufacturing method of a solder ball disposing surface structure on a core board including: providing a core board with a first metal layer and an opposing... |
| US-7,544,598 |
Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device, including: providing a semiconductor substrate which has a plurality of electrodes and in which a depression is... |
| US-7,544,597 |
Method of forming a semiconductor device including an ohmic layer In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer... |
| US-7,544,596 |
Atomic layer deposition of GdScO3 films as gate dielectrics The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of gadolinium oxide (Gd.sub.2O.sub.3) and scandium oxide (Sc.sub.2O.sub.3) acting as a... |
| US-7,544,595 |
Forming a semiconductor device having a metal electrode and structure
thereof A method for forming a semiconductor device includes forming a gate dielectric over a substrate, forming a metal electrode over the gate dielectric, forming a... |
| US-7,544,594 |
Method of forming a transistor having gate protection and transistor
formed according to the method A microelectronic device and a method of forming same. The method comprises: a transistor gate; a first spacer and a second spacer respectively adjacent a first... |
| US-7,544,593 |
Semiconductor device having a gate insulating film structure including an
insulating film containing metal,... Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound,... |
| US-7,544,592 |
Method for increasing etch rate during deep silicon dry etch A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of... |
| US-7,544,591 |
Method of creating isolated electrodes in a nanowire-based device Methods of creating isolated electrodes and integrating a nanowire therebetween each employ lateral epitaxial overgrowth of a semiconductor material on a... |
| US-7,544,590 |
Wafer laser processing method A method of carrying out laser processing on a wafer having a plurality of parallel streets on the front surface along the streets, comprising the steps of: ... |
| US-7,544,589 |
Wafer dividing method A method of dividing a wafer having a plurality of devices, which are formed in a plurality of areas sectioned by streets formed in a lattice pattern on the... |
| US-7,544,588 |
Laser processing method for wafer Disclosed herein is a laser processing method for a wafer having a plurality of regions defined by streets, with the regions having a plurality of devices formed... |
| US-7,544,587 |
Wafer dividing method and wafer dividing apparatus A method of dividing, along lattice pattern-like dividing lines, a wafer which has the lattice pattern-like dividing lines and a polymer film on the front... |
| US-7,544,586 |
Method of fabricating chips and an associated support A method of fabricating a plurality of chips, with each chip including at least one circuit. This method includes the successive steps of creating chips on a... |
| US-7,544,585 |
Structure of strained silicon on insulator and method of manufacturing the
same Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a... |
| US-7,544,584 |
Localized compressive strained semiconductor One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline... |
| US-7,544,583 |
SOI wafer and its manufacturing method Since a supporting wafer contains nitrogen of 1.times.10.sup.14 atmos/cm.sup.3 and interstitial oxygen atom concentration, Oi, (old ASTM) of 13.times.10.sup.17... |
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