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| Patent # | Description |
|---|---|
| US-7,546,442 |
Fixed length memory to memory arithmetic and architecture for direct
memory access using fixed length instructions A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for... |
| US-7,546,441 |
Coprocessor interface controller A controller interface between a processor and a coprocessor is described. The controller is coupled to the processor to provide a processor interface for... |
| US-7,546,440 |
Non-volatile memory devices and control and operation thereof An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended... |
| US-7,546,439 |
System and method for managing copy-on-write faults and change-protection A method of identifying a shared main memory page containing a physical address corresponding to a virtual address included in an issued write instruction. The... |
| US-7,546,438 |
Algorithm mapping, specialized instructions and architecture features for
smart memory computing A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the... |
| US-7,546,437 |
Memory usable in cache mode or scratch pad mode to reduce the frequency of
memory accesses A processor adapted to couple to external memory. The processor comprises a controller and data storage (e.g., cache memory). The data storage is configurable to... |
| US-7,546,436 |
Storage device with SCSI formatting Provided are a method, system, and an article of manufacture for detecting errors while accessing a storage device. A host system writes an identical... |
| US-7,546,435 |
Dynamic command and/or address mirroring system and method for memory
modules A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The... |
| US-7,546,434 |
Method to write data to an information storage and retrieval system A method is disclosed to write data to an information storage and retrieval system comprising (n) volumes and a data cache, where that information storage and... |
| US-7,546,433 |
Storage system, and data management and migration method A storage system or data management and migration method enabling migration of an access destination for a host system without having to stop the transmission of... |
| US-7,546,432 |
Pass-through write policies of files in distributed storage management A hierarchical storage system includes file servers and a policy engine server. Offline attributes are added to file system inodes in a primary file server, file... |
| US-7,546,431 |
Distributed open writable snapshot copy facility using file migration
policies A read-write snapshot copy facility is constructed from a hierarchical storage management facility. The read-write snapshot copy file system initially comprises... |
| US-7,546,430 |
Method of address space layout randomization for windows operating systems A system and method for address space layout randomization ("ASLR") for a Windows operating system is disclosed. The address space layout includes one or more... |
| US-7,546,429 |
Method of detection of data corruption in mirrored storage A first read request is received from a computer system. Data from one mirror of a data volume is returned to the computer system in response to receiving the... |
| US-7,546,428 |
Computer architecture for managing replication of data in a data storage
environment This invention is an architecture for backup and recovery of data including continuous backup and information protection backup and recovery system components. |
| US-7,546,427 |
System for rebuilding dispersed data A digital data file storage system is disclosed in which original data files to be stored are dispersed using some form of information dispersal algorithm into a... |
| US-7,546,426 |
Storage having a logical partitioning capability and systems which include
the storage A storage includes: host interface units; file control processors which receives a file input/output request and translates the file input/output request into a... |
| US-7,546,425 |
Data processor with a built-in memory A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing... |
| US-7,546,424 |
Embedded processor with dual-port SRAM for programmable logic Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a... |
| US-7,546,423 |
Signal processing system control method and apparatus A signal processing system control method and apparatus are described. Various embodiments include a signal processing system with multiple subsystems. A method... |
| US-7,546,422 |
Method and apparatus for the synchronization of distributed caches A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a... |
| US-7,546,421 |
Interconnect transaction translation technique A technique to reduce and simplify interconnect traffic within a multi-core processor. At least one embodiment translates two or more system operations destined... |
| US-7,546,420 |
Efficient trace cache management during self-modifying code processing Efficient trace cache management during self-modifying code processing enables selective invalidation of entries of the trace cache, advantageously retaining... |
| US-7,546,419 |
Efficient data cache A method is disclosed which may include providing a cache in a computing system having an initial group of cache objects, the cache object having an initial... |
| US-7,546,418 |
System and method for managing power consumption and data integrity in a
computer system A system and method for managing power consumption and data integrity in a computer system is disclosed in which the a memory controller of the computer system... |
| US-7,546,417 |
Method and system for reducing cache tag bits A method of accessing data from a cache is disclosed. Tag bits of data among sets and ways of cache lines are divided into common subtags and remaining subtags.... |
| US-7,546,416 |
Method for substantially uninterrupted cache readout A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring... |
| US-7,546,415 |
Apparatus, system, and method for integrating multiple raid storage
instances within a blade center An apparatus, system, and method are disclosed for integrating redundant array of independent disk ("RAID") storage within a blade center. A plurality of... |
| US-7,546,414 |
Computer system, storage system, and device control method The invention provides a computer system, storage system, and device control method which keep and operate long-term data stored in a disk device using its... |
| US-7,546,413 |
Apparatus and method for managing a plurality of kinds of storage devices A storage system including a memory unit having a disk management program, plural disk controllers each having a SAS port which can be attached to either a SAS... |
| US-7,546,412 |
Apparatus, system, and method for global metadata copy repair An apparatus, system, and method are disclosed for global metadata copy repair. The apparatus includes a control module for copying global metadata from primary... |
| US-7,546,411 |
Digital device configuration and method An electromechanical data storage arrangement is interfaced with a host. The interface may include a conductor that carries read and write gate signals. Another... |
| US-7,546,410 |
Self timed memory chip having an apportionable data bus A self timed memory chip having an apportionable data bus. Access timing to an array on the memory chip is dynamically determined by circuitry on the memory... |
| US-7,546,409 |
Deferring peripheral traffic with sideband control In some embodiments, a system comprises a USB host system comprising a USB function driver, and a USB device coupled to the USB host system via a USB interface,... |
| US-7,546,408 |
Method and apparatus for communication within a programmable device using
serial transceivers Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a... |
| US-7,546,407 |
Flexible wiring system for electronic apparatus A flexible wiring system for an electronic system includes an intermediate distributing unit and a changeover control unit. The intermediate distributing unit... |
| US-7,546,406 |
Virtualization of a global interrupt queue A method, system, and article of manufacture for processing virtual interrupts in a logically partitioned system are provided. An intelligent virtual global... |
| US-7,546,405 |
Methods and apparatus for dynamic grouping of requestors of resources in a
multi-processor system Methods and apparatus provide for: assigning each of a plurality of requesters to a respective one of a plurality of requester groups; receiving tokens from a... |
| US-7,546,404 |
Method and apparatus for arbitration in a wireless device A method and apparatus for traffic arbitration in a system are provided. In the system, a first module operating in a first protocol and a second module... |
| US-7,546,403 |
Method and apparatus for a disc drive client interface Aspects of the invention include a method and apparatus to transfer specific data files from a disc drive storage system to an output device such as a printer.... |
| US-7,546,402 |
Optical storage system comprising interface for transferring data An optical storage system for coupling to at least a plurality of peripheral devices. The optical storage system includes a data read subsystem to read out data... |
| US-7,546,401 |
Byte to byte alignment of multi-path data Methods and apparatus that may be utilized in an effort to ensure bytes of data sequentially received on multiple single-byte data paths with properly aligned... |
| US-7,546,400 |
Data packet buffering system with automatic threshold optimization Data packet buffering system comprising a data buffer for buffering data packets, a first counter (24) preloaded with the data packet size (32) and decremented... |
| US-7,546,399 |
Store and forward device utilizing cache to store status information for
active queues In general, in one aspect, the disclosure describes an apparatus capable of queuing and de-queuing data stored in a plurality of queues. The apparatus includes a... |
| US-7,546,398 |
System and method for distributing virtual input/output operations across
multiple logical partitions The Distributed Virtual I/O Tool replaces dedicated VIO server LPARs by distributing the virtual I/O functions across several application LPARs connected by a... |
| US-7,546,397 |
Systems and methods for allowing multiple devices to share the same serial
lines Methods and systems for allowing multiple devices to share the same serial lines (e.g., SDIO, SEN and SCLK) are provided. Such devices can be located, e.g., on... |
| US-7,546,396 |
Interface system A data transfer interface is provided which enables a plurality of data processing devices to access a single data storage drive. The data processing device... |
| US-7,546,395 |
Navagation processing between a tracker hardware device and a computer
host based on a satellite positioning... Methods and systems consistent with the present invention provide a host based positioning system. The host based positioning system includes a tracker hardware... |
| US-7,546,394 |
Management of configuration data by generating a chain description data
set that specifies an order of... Methods and apparatus are disclosed for managing configuration data for a system. In various embodiments, a chain description data set is generated to specify an... |
| US-7,546,393 |
System for asynchronous DMA command completion notification wherein the
DMA command comprising a tag belongs to... The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a... |
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