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| Patent # | Description |
|---|---|
| US-7,554,885 |
Polarization diversity for optical fiber applications At least two light beams with polarization diversity are generated that each carry a representation of the same information. Separate optic fibers carry each of... |
| US-7,554,884 |
Simplicity sonic depth finder for fishing Provided is a detector for fishing in order to detect the depth of water, the temperature of water, the distribution of fishes including fishes' migration and/or... |
| US-7,554,883 |
Fault filter for seismic discontinuity data Various methods are disclosed for identifying faults in a seismic data volume. In some method embodiments, the fault identification method comprises determining... |
| US-7,554,882 |
Methods and systems for calibrating acoustic receivers A method for in-situ calibrating acoustic receivers while the tool is in an open or cased borehole or during a logging run in a borehole. The method and system... |
| US-7,554,881 |
Determining seawater conductivity for the compensation of
electromagnetics-based survey data A technique includes obtaining seismic data, which was acquired during a seismic survey in seawater. The technique includes based on the seismic data,... |
| US-7,554,880 |
Marine surveys A method generates at least one route traversing a plurality of predetermined survey paths in a marine survey. The method includes generating a plurality of... |
| US-7,554,879 |
Apparatus for testing a nonvolatile memory and a method thereof An apparatus for testing or programming a nonvolatile memory in a micro control system and a method thereof is provided. The micro control system comprises: a... |
| US-7,554,878 |
Synchronous memory device A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in... |
| US-7,554,877 |
Apparatus and method for data outputting An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a... |
| US-7,554,876 |
Semiconductor memory device A semiconductor memory device can effectively select a word line. The semiconductor memory device includes a word line driver unit for including N unit driving... |
| US-7,554,875 |
Bus structure, memory chip and integrated circuit A bus structure comprises a plurality of driver circuits, each driver circuit comprising an input for a first signal and a terminal for an output signal wherein... |
| US-7,554,874 |
Method and apparatus for mapping memory A memory mapping method is provided for writing block data composed of a plurality of lines in first and second memories, each memory including at least two... |
| US-7,554,873 |
Three-dimensional memory devices and methods of manufacturing and
operating the same A memory device includes a plurality of planes of memory arrays, each memory array including a plurality of memory cells. The memory device also includes a... |
| US-7,554,872 |
Semiconductor device including multi-chip In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control... |
| US-7,554,871 |
Semiconductor memory apparatus A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second... |
| US-7,554,870 |
DRAM with reduced power consumption In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of rows of memory cells, each of the memory cell rows being... |
| US-7,554,869 |
Semiconductor memory device having internal circuits responsive to
temperature data and method thereof A semiconductor memory device having internal circuits responsive to temperature data, in order to compensate an output characteristic change of the internal... |
| US-7,554,868 |
Semiconductor memory device A semiconductor memory cell is implemented in which the area of a row selection circuit is reduced and the effects of exposure, etching, and so on performed... |
| US-7,554,867 |
Capacitor boost sensing A memory cell for storing a charge that gives rise to a cell voltage representing a bit value, the memory cell being capable of having the cell voltage boosted... |
| US-7,554,866 |
Circuit and method of controlling input/output sense amplifier of a
semiconductor memory device An input/output sense amplifier (IOSA) controller of a semiconductor memory device includes an auto pulse generator and a latch enable signal generating circuit.... |
| US-7,554,865 |
Randomizing current consumption in memory devices In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that... |
| US-7,554,864 |
Semiconductor memory device including a global input/output line of a data
transfer path and its surrounding... A semiconductor memory device includes an input/output line of a data transfer path and its surrounding circuits, comprising a controller which generates a... |
| US-7,554,863 |
Voltage control circuit and semiconductor device having the voltage
control circuit A voltage control circuit of the present invention is applicable to a combination of a decoder circuit and a level conversion circuit connected to the decoder... |
| US-7,554,862 |
High-speed writable semiconductor memory device A memory cell array has a plurality of series connected memory cells connected to word lines and bit lines and arranged in a matrix. A select transistor selects... |
| US-7,554,861 |
Memory device with a ramp-like voltage biasing structure and reduced
number of reference cells A memory device is proposed. The memory device includes a plurality of memory cells, means for comparing a set of selected memory cells with at least one... |
| US-7,554,860 |
Nonvolatile memory integrated circuit having assembly buffer and bit-line
driver, and method of operation thereof An assembly buffer and bitline driver circuit has two inverters cross-coupled to form an assembly buffer. A high-voltage latch is formed from cross-coupled... |
| US-7,554,859 |
Nonvolatile memory system and associated programming methods A nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells. The memory controller... |
| US-7,554,858 |
System and method for reducing pin-count of memory devices, and memory
device testers for same Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output... |
| US-7,554,857 |
Data output multiplexer A data output multiplexer for multiplexing and transferring data of a data input/output (I/O) line includes a first latch unit coupled to the data I/O line to... |
| US-7,554,856 |
Memory cell A method of reading memory includes sensing a plurality of memory cells simultaneously and providing a data signal corresponding to one of a plurality of... |
| US-7,554,855 |
Hybrid solid-state memory system having volatile and non-volatile memory A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile... |
| US-7,554,854 |
Method for deleting data from NAND type nonvolatile memory To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate... |
| US-7,554,853 |
Non-volatile storage with bias based on selective word line A non-volatile storage system in which a body bias is applied to compensate for performance variations which are based on the position of a selected word line... |
| US-7,554,852 |
Method of erasing flash memory with pre-programming memory cells only in
the presence of a cell leakage Some embodiments include converting a plurality of memory cells into a first logic state, and converting the plurality of memory cells into a second logic state... |
| US-7,554,851 |
Reset method of non-volatile memory A reset method of a non-volatile memory is described. The non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each... |
| US-7,554,850 |
Nonvolatile memory device with load-supplying wired-or structure and an
associated driving method We describe a nonvolatile memory device with a wired-OR structure and method of driving the same that reduces peak current during the wired-OR operation. The... |
| US-7,554,849 |
Nonvolatile semiconductor memory A nonvolatile semiconductor memory for setting control voltages to be supplied to an internal circuit, to an external reference voltage inputted from outside,... |
| US-7,554,848 |
Operating techniques for reducing program and read disturbs of a
non-volatile memory The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing... |
| US-7,554,847 |
Flash memory device employing disturbance monitoring scheme A flash memory device comprises a memory cell array including a plurality of NAND strings respectively connected to a plurality of bit lines, and further... |
| US-7,554,846 |
Select gate transistors and methods of operating the same Memory arrays, methods and cells are disclosed, such as those involving a floating gate memory array having a plurality of transistors arranged in a plurality of... |
| US-7,554,845 |
EEPROM cell and EEPROM block The EEPROM cell includes a writing unit having a flash cell Metal Oxide Semiconductor (MOS) for receiving from outside a gate selection signal via a gate and a... |
| US-7,554,844 |
Integrated circuit with analog or multilevel storage cells and
user-selectable sampling frequency Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The... |
| US-7,554,843 |
Serial bus incorporating high voltage programming signals A serial bus which comprises two wires (a clock signal and a data signal), one of which transmits high voltages in addition to the two-level voltages used for... |
| US-7,554,842 |
Multi-purpose non-volatile memory card A flash non-volatile memory system that normally operates its memory cells in multiple storage states is provided with the ability to operate some selected or... |
| US-7,554,841 |
Circuit for storing information in an integrated circuit and method
therefor A circuit has a storing portion, a write portion and a read portion. In one embodiment, read portion has a transistor which has a substantially thinner gate... |
| US-7,554,840 |
Semiconductor device and fabrication thereof A memory device is disclosed. A floating gate is disposed overlying a substrate. A tunneling dielectric layer is interposed between the floating gate and the... |
| US-7,554,839 |
Symmetric blocking transient voltage suppressor (TVS) using bipolar
transistor base snatch A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically... |
| US-7,554,838 |
Simulating circuit for magnetic tunnel junction device A simulating circuit for simulating the operation of a magnetic tunnel junction (MTJ) device having at least a free layer and a fixed layer is provided. The... |
| US-7,554,837 |
Magnetic memory device A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center... |
| US-7,554,836 |
Data write in control circuit for toggle magnetic random access memory A data write in control circuit for magnetic random access memory is configured with a first transistor, a second transistor connected to the first transistor, a... |
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