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| Patent # | Description |
|---|---|
| US-7,555,637 |
Multi-port read/write operations based on register bits set for indicating
select ports and transfer directions A computer (12) having multiple data paths (38a-d) connecting to other devices, which may be similar computers. A register (40d) is provided that has bits (110)... |
| US-7,555,636 |
Atomically updating 64 bit fields in the 32 bit AIX kernel A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable... |
| US-7,555,635 |
Data processing device A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an... |
| US-7,555,634 |
Multiple data hazards detection and resolution unit Order indication logic can be recycled for at least two different data hazards, thus reducing the amount of processor real estate consumed by data hazard... |
| US-7,555,633 |
Instruction cache prefetch based on trace cache eviction Various embodiments of methods and systems for implementing a microprocessor that fetches a group of instructions into instruction cache in response to a... |
| US-7,555,632 |
High-performance superscalar-based computer system with out-of-order
instruction execution and concurrent... The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and... |
| US-7,555,631 |
RISC microprocessor architecture implementing multiple typed register sets A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data... |
| US-7,555,630 |
Method and apparatus to provide efficient communication between
multi-threaded processing elements in a... A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements.... |
| US-7,555,629 |
Memory card providing hardware acceleration for read operations A memory card comprises a memory controller connected to a non-volatile memory module. The memory controller comprises a first circuit adapted to convert a first... |
| US-7,555,628 |
Synchronizing a translation lookaside buffer to an extended paging table A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest... |
| US-7,555,627 |
Input-output control apparatus, input-output control method, process
control apparatus and process control method Input-output devices are prevented from conducting false output due to faulty operation by providing an input-output control apparatus configured to store... |
| US-7,555,626 |
Information reproducing apparatus, data management information obtaining
method, data management information... An information reproducing apparatus reproducing information of an information recording medium is disclosed. In the information recording medium, a record area... |
| US-7,555,625 |
Multi-memory chip and data transfer method capable of directly
transferring data between internal memory devices A multi-memory chip and data transfer method are capable of directly transferring data between internal memory devices. The multi-memory chip of the present... |
| US-7,555,624 |
Program, an apparatus and a method for guaranteeing a data storage order
in an ISAM file When a data storage request is issued, data is stored at an address indicated by a pointer that indicates the start of a free area, and when a data fetch request... |
| US-7,555,623 |
Arrangements changing an operation authority responsive to attribute
changes A volume management system, a managing computer, a host, and a volume management method being capable of regulating the authorities of users and avoiding... |
| US-7,555,622 |
Method and apparatus for increasing an amount of memory on demand when
monitoring remote mirroring performance A method and storage system for increasing an amount of memory in a queuing area on. The storage system includes first and second storage subsystems connected to... |
| US-7,555,621 |
Disk access antiblocking system and method A system, method and computer program product that manage storage device load, including (a) classifying processes that access a storage device as high priority... |
| US-7,555,620 |
Method and system of using a backup image for multiple purposes A method for utilizing a backup image of a dataset for multiple purposes, including modifying or deleting any data thereof, yet without changing or modifying the... |
| US-7,555,619 |
Efficient per-object operations in software transactional memory A software transactional memory system is described which utilizes decomposed software transactional memory instructions as well as runtime optimizations to... |
| US-7,555,618 |
Assuring genuineness of data stored on a storage device Techniques to assure genuineness of data stored on a storage device are provided. The storage device includes a storage controller that conducts I/O operations... |
| US-7,555,617 |
Electronic data processing device with secured memory access An electronic data processing device includes a data processing member provided for controlling, based on first and second encoded data, a secured operation... |
| US-7,555,616 |
Devices and methods for memory tag error correction Embodiments relating to a memory tag having a resonant circuit part and a non-volatile memory is presented. The resonant circuit part can be made operable, in... |
| US-7,555,615 |
Product demonstration system and method for using same The product demonstration system of the present invention is used to familiarize a person with a product. The product demonstration system includes an... |
| US-7,555,614 |
Methods, systems, and computer program products for preventing concurrent
execution of conflicting software... Methods, systems, and computer program products for preventing concurrent execution of conflicting software operations on the same and different storage... |
| US-7,555,613 |
Storage access prioritization using a data storage device Herein described is a method and system of prioritizing access to data stored in one or more data processing devices communicatively coupled to the data storage... |
| US-7,555,612 |
Adaptive control of loading a program in a disk-based operating system An exemplary method controls the loading of a program in a computer system using a disk based operating system instead of allowing a built-in loading program... |
| US-7,555,611 |
Memory management of local variables upon a change of context A cache subsystem may comprise a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a... |
| US-7,555,610 |
Cache memory and control method thereof The cache memory in the present invention includes a C flag setting unit 40 which adds, to each cache entry holding line data, a cleaning flag C indicating... |
| US-7,555,609 |
Systems and method for improved data retrieval from memory on behalf of
bus masters Systems and methods are disclosed herein for retrieving data from memory in a computer system. In one example, a memory controller is coupled to a system bus in... |
| US-7,555,608 |
Techniques to manage a flow cache Techniques are described herein that may be used to invalidate all entries in a table. For example, the table may be a flow cache. For example, an expiry time... |
| US-7,555,607 |
Program thread syncronization for instruction cachelines In a method of and system for program thread synchronization, an instruction cache line is determined each of a plurality of program threads to be synchronized.... |
| US-7,555,606 |
System and method for caching results In certain aspects, the invention features a system and method for caching results, including receiving a job for computation by a distributed computing system... |
| US-7,555,605 |
Data processing system having cache memory debugging support and method
therefor A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache... |
| US-7,555,604 |
Method and structure for an improved data reformatting procedure A method (and structure) of managing memory in which a low-level mechanism is executed to signal, in a sequence of instructions generated at a higher level, that... |
| US-7,555,603 |
Transaction manager and cache for processing agent A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal... |
| US-7,555,602 |
Data processing apparatus and method for restoring a file system A data processing apparatus for writing data to a recording medium having a predetermined file system configured therein includes the following elements: an... |
| US-7,555,601 |
Storage control system including virtualization and control method for
same A storage control system judges whether the data pattern of data exchanged with a higher-level device (hereafter "data") conforms to one or a plurality of... |
| US-7,555,600 |
Storage apparatus and configuration setting method This storage apparatus has a plurality of physical devices for storing data sent from a host system, and includes a physical device group setting unit for... |
| US-7,555,599 |
System and method of mirrored RAID array write management The write operations to the storage devices are managed so that the write operations that would force a storage device to reposition its read/write head outside... |
| US-7,555,598 |
RAID systems and setup methods thereof that integrate several RAID 0
architectures RAID systems and setup methods thereof are provided. At least a first group of disks is selected to create a RAID 0 architecture. A second group of disks is... |
| US-7,555,597 |
Direct cache access in multiple core processors Methods and apparatus to perform direct cache access in multiple core processors are described. In an embodiment, data corresponding to a direct cache access... |
| US-7,555,596 |
Systems and methods for attaching a virtual machine virtual hard disk to a
host machine Various embodiments of the present invention are directed to systems and methods for "attaching" a virtual hard drive to the physical computer hardware by... |
| US-7,555,595 |
Methods and apparatus for writing servo frames to and/or verifying data
areas of a storage medium Methods and apparatus are disclosed for writing and verifying servo frames written on a storage medium, for verifying data areas of a storage medium, and for... |
| US-7,555,594 |
Range representation in a content addressable memory (CAM) using an
improved encoding scheme In a method and apparatus for encoding a bit field within a memory device, the bit field is encoded in a manner that requires fewer memory device entries and... |
| US-7,555,593 |
Simultaneous multi-threading in a content addressable memory A CAM device having two execution pipelines includes control logic and a CAM core. The CAM core includes a plurality of independently searchable CAM arrays for... |
| US-7,555,592 |
Kernel acceleration technology for virtual machine optimization A system, method and computer program product for optimizing handling of guest code in a Virtual Machine include code for identifying, in the guest code, a... |
| US-7,555,591 |
Method and system of memory management The disclosure is directed to a computational system including a processor, cache memory accessible to the processor, and a memory management unit accessible to... |
| US-7,555,590 |
Fast buffer pointer across clock domains Retiming circuitry for retiming a data signal transmitted from a first environment under control of a first clock signal to a second environment under control of... |
| US-7,555,589 |
Multi-protocol serial interface system A multi-protocol serial interface system comprises a multi-protocol port pin array, a transport protocol change FPGA, a pull-up change FPGA and a memory. The... |
| US-7,555,588 |
Computers having USB buses, methods of operation thereof and programs and
information for use therewith A computer has a USB bus with at least two USB connectors for removable USB devices. When a removable USB device is connected to at least one of the connectors,... |
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