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| Patent # | Description |
|---|---|
| US-7,553,783 |
Cleaning sheet Disclosed is a cleaning sheet which has low frictional resistance to an object to be cleaned and is effective in removing various types of dirt and dust when... |
| US-7,553,782 |
Flame-resistant high visibility textile fabric for use in safety apparel A knitted textile fabric for use in safety apparel, comprising a first yarn containing modacrylic fibers and a second yarn containing cellulosic fibers. The... |
| US-7,553,781 |
Fabrics with high thermal conductivity coatings The present invention facilitates the thermal conductivity of fabrics by surface coating of the fabrics with high thermal conductivity materials 6. The fabrics... |
| US-7,553,780 |
Gypsum panel having UV-cured moisture resistant coating and method for
making the same A fibrous mat faced gypsum panel having on at least one of the facing sheets a moisture resistant, cured coating of a radiation curable, e.g., UV curable, polymer. |
| US-7,553,779 |
Protective laminates Protective laminates are provided that include (a) a layer that is breathable and highly impermeable to chemicals to a degree that is subject to reduction upon... |
| US-7,553,778 |
Method for producing a semiconductor device including crystallizing an
amphorous semiconductor film A method for producing a semiconductor device includes irradiating an amorphous semiconductor film on an insulating material with a pulsed laser beam having a... |
| US-7,553,777 |
Silicon wafer laser processing method and laser beam processing machine A silicon wafer laser processing method for forming a deteriorated layer along dividing lines formed on a silicon wafer in the inside of the silicon wafer by... |
| US-7,553,776 |
Patterned functionalized silicon surfaces The present invention provides a method for preparing a silicon substrate and a silicon substrate having a silicon surface comprising a pattern of covalently... |
| US-7,553,775 |
Method for coating semiconductor surface, process for production of
semiconductor particles using said method,... The present invention provides a method for coating a group 4 semiconductor surface composed mainly of a group 4 semiconductor elements and a process for... |
| US-7,553,774 |
Method of fabricating semiconductor optical device In a method of fabricating a semiconductor optical device, insulating structures for an alignment mark for use in electron beam exposure are formed on a primary... |
| US-7,553,773 |
Pressure control method and processing device First and second pressure sensors 132 and 134 that perform pressure detection over different pressure detection ranges from each other detect the pressure within... |
| US-7,553,772 |
Process and apparatus for simultaneous light and radical surface treatment
of integrated circuit structure Process and apparatus provide reactive radicals generated from a remote plasma source which contact a portion of a substrate surface simultaneous with a contact... |
| US-7,553,771 |
Method of forming pattern of semiconductor device A method of forming a pattern of a semiconductor device comprises forming a first hard mask film, a first resist film, and a second hard mask film over an... |
| US-7,553,770 |
Reverse masking profile improvements in high aspect ratio etch A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of... |
| US-7,553,769 |
Method for treating a dielectric film A method and system for treating a dielectric film includes exposing at least one surface of the dielectric film to a C.sub.xH.sub.y containing material, wherein... |
| US-7,553,768 |
Substrate and a method for polishing a substrate A substrate having flatness of less than 230 nmPV and surface roughness at RMS of less than 0.20 nm. is obtained by a method comprising: a process of polishing... |
| US-7,553,767 |
Method for fabricating semiconductor device having taper type trench A method for fabricating a semiconductor includes: etching a substrate to a predetermined depth to form an upper trench with taper edges; etching the substrate... |
| US-7,553,766 |
Method of fabricating semiconductor integrated circuit device A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by... |
| US-7,553,765 |
Method of manufacturing thin-film electronic device having a through-hole
extending through the base and in... A method of manufacturing a thin-film electronic device comprising providing a dielectric layer on a base, providing a first electrically conductive layer having... |
| US-7,553,764 |
Silicon wafer having through-wafer vias A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. A... |
| US-7,553,763 |
Salicide process utilizing a cluster ion implantation process A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process... |
| US-7,553,762 |
Method for forming metal silicide layer The invention provides a method for forming a metal silicide layer. The method comprises steps of providing a substrate and forming a nickel-noble metal layer... |
| US-7,553,761 |
Method of fabricating semiconductor device A method of fabricating a semiconductor device is provided. The method includes forming a low-k dielectric layer on a semiconductor substrate, forming a mask... |
| US-7,553,760 |
Sub-lithographic nano interconnect structures, and method for forming same A method to form interconnect structures including nano-scale, e.g., sub-lithographic, lines and vias for future generation of semiconductor technology using... |
| US-7,553,759 |
Semiconductor device and method of manufacturing a semiconductor device A semiconductor device may include the following. A diffusion barrier formed over a semiconductor substrate having a conductive layer. An etching stop layer... |
| US-7,553,758 |
Method of fabricating interconnections of microelectronic device using
dual damascene process Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic... |
| US-7,553,757 |
Semiconductor device and method of manufacturing the same An interlayer insulator includes a first interlayer insulator and a second interlayer insulator formed on the first interlayer insulator and having a property of... |
| US-7,553,756 |
Process for producing semiconductor integrated circuit device An object of the present invention is to prevent formation of a badly situated via metal in a Damascene wiring portion in multiple layers having an air-gap... |
| US-7,553,755 |
Method for symmetric deposition of metal layer A method for symmetric deposition of metal layer over a metal layer registration key comprises using MOCVD to form the metal layer. Once the symmetric metal... |
| US-7,553,754 |
Electronic device, method of manufacture of the same, and sputtering
target In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted... |
| US-7,553,753 |
Method of forming crack arrest features in embedded device build-up
package and package thereof A method of forming an embedded device build-up package (10) includes forming a first plurality of features (22) over a packaging substrate (12,16,18), wherein... |
| US-7,553,752 |
Method of making a wafer level integration package A semiconductor package is made by providing a wafer having a first electrical contact pad integrated into a top surface of the wafer, forming a through-hole... |
| US-7,553,751 |
Method of forming solder bump with reduced surface defects A method of forming a solder bump may involve forming a first photoresist pattern on a wafer having a pad. The first photoresist pattern may have an opening that... |
| US-7,553,750 |
Method for fabricating electrical conductive structure of circuit board A method for fabricating an electrical conductive structure of a circuit board is disclosed. The method includes providing a circuit board having a plurality of... |
| US-7,553,749 |
Method of hiding transparent electrodes on a transparent substrate A method of hiding transparent electrodes on a transparent substrate coats a solution of non-conductive nanoparticles onto the transparent substrate and the... |
| US-7,553,748 |
Semiconductor device and method of manufacturing the same According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to... |
| US-7,553,747 |
Schottky diode having a nitride semiconductor material and method for
fabricating the same A Schottky diode includes a first nitride semiconductor layer formed on a substrate and a second nitride semiconductor layer selectively formed on the first... |
| US-7,553,746 |
Method for manufacturing electrodes on a semiconducting material of type
II-VI or on a compound of this material A method for manufacturing electrodes on a semiconducting material of type II-VI or on a compound of this material. The electrodes are preferably in gold or... |
| US-7,553,745 |
Integrated circuit package, panel and methods of manufacturing the same A method of manufacturing an integrated circuit package includes: assembling a composite wafer including alternating rows or columns of first and second strips... |
| US-7,553,744 |
Method for low temperature bonding and bonded structure A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also... |
| US-7,553,743 |
Wafer bonding method of system in package A method of bonding a wafer in a system in package is provided. A plating layer is formed on each of a first semiconductor substrate and a second semiconductor... |
| US-7,553,742 |
Method(s) of forming a thin layer A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and... |
| US-7,553,741 |
Manufacturing method of semiconductor device Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the... |
| US-7,553,740 |
Structure and method for forming a minimum pitch trench-gate FET with
heavy body region A field effect transistor is formed as follows. Openings are formed in a masking layer extending over a surface of a silicon region. A trench is formed in the... |
| US-7,553,739 |
Integration control and reliability enhancement of interconnect air
cavities An improved semiconductor device, integrated circuit, and integrated circuit fabrication method introduce highly controlled air cavities within high-speed copper... |
| US-7,553,738 |
Method of fabricating a microelectronic device including embedded thin
film capacitor by over-etching thin film... A microelectronic device, a method of fabricating the device, and a system including the device. The method includes: providing a substrate including an... |
| US-7,553,737 |
Method for fabricating recessed-gate MOS transistor device A method of fabricating gate trench utilizing pad pullback technology is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad layer is... |
| US-7,553,736 |
Increasing dielectric constant in local regions for the formation of
capacitors A method for increasing capacitances of capacitors and the resulting integrated structure are provided. The method includes providing a substrate, forming a... |
| US-7,553,735 |
Scalable high performance non-volatile memory cells using multi-mechanism
carrier transport A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate... |
| US-7,553,734 |
Method for forming an avalanche photodiode Methods for fabricating an avalanche photodiode (APD), wherein the APD provides both high optical coupling efficiency and low dark count rate. The APD is formed... |
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