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Patent # Description
US-9,564,935 Linear composite transmitter utilizing composite power amplification
The present invention provides a compound transmitter having power efficiency characteristics and distortion characteristics superior, over a wide band, to...
US-9,564,934 Telecontrol for automobile comprising a device for suppressing magnetic coupling
The invention relates to a telecontrol (TEL) for the locking/unlocking and the starting of a motor vehicle comprising: --an electronic circuit (ELEC) comprising...
US-9,564,933 Wireless communication method and wireless communication apparatus
A wireless communication method is provided. This method includes: selecting one of a plurality of predetermined frequency bands each time a switch operation is...
US-9,564,932 Software defined radio front end
The present application describes a computer-implemented method for configuring a front end including sweeping a first tone through the frequency band of the...
US-9,564,931 Systems and methods for using decoders of different complexity in a hybrid decoder architecture
Systems and methods are provided for decoding a codeword having a first codeword length using a decoding system. The systems and methods include receiving a...
US-9,564,930 Memory controller, storage device and memory control method
According to one embodiment, a memory controller includes an encoding unit that generates a first code word, a duplication unit that duplicates the first code...
US-9,564,929 Parallel bit interleaver
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the...
US-9,564,928 Transmitter and method for generating additional parity thereof
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword...
US-9,564,927 Constrained interleaving for 5G wireless and optical transport networks
The present invention provides a design framework that is used to develop new types of constrained turbo block convolutional (CTBC) codes that have higher...
US-9,564,926 Time varying data permutation apparatus and methods
Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data...
US-9,564,925 Pipelined architecture for iterative decoding of product codes
In one embodiment, a method includes loading first data into a first buffer of an interposer during a first time period and loading second data into a second...
US-9,564,924 Apparatus and method for designing quantum code
Provided is an apparatus for designing a quantum code, which includes an analyzing unit for analyzing at least one quantum error generated in a quantum error...
US-9,564,923 Reception apparatus and associated method of receiving encoded data
A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit...
US-9,564,922 Error correction code decoder with stochastic floor mitigation
A method and apparatus as described herein provide a novel modification to any iterative FEC decoder method that can improve FER performance in the error floor...
US-9,564,921 Method and system for forward error correction decoding based on a revised error channel estimate
An FEC codeword comprises channel information indicating the reliability of the information contained by the FEC codeword. The channel information can be used...
US-9,564,920 Method and apparatus for mitigation of false packet decodes due to early decoding
Methods and apparatus for wireless communication in a wireless communication network include determining a transmit data packet size at a transmitting device...
US-9,564,919 Managing data records
Data records may be managed in a relational database by monitoring, a record length for a first data record in a page of memory, an amount of free space in the...
US-9,564,918 Real-time reduction of CPU overhead for data compression
Real-time reduction of CPU overhead for data compression is performed by a processor device in a computing environment. Non-compressing heuristics are applied...
US-9,564,917 Instruction and logic for accelerated compressed data decoding
A processor includes an execution unit to decode compressed data. The execution unit includes a code information array, a matching logic unit, a code value...
US-9,564,916 Suppressing signal transfer function peaking in a feedforward delta sigma converter
A modified topology for a CTDSM (referred herein as "SCFF") can effectively deal with signal transfer function (STF) peaking, an inherent property of continuous...
US-9,564,915 Apparatus for data converter with internal trigger circuitry and associated methods
An integrated circuit (IC) includes an analog-to-digital converter (ADC). The ADC includes an ADC core circuit integrated in the IC to receive an analog signal,...
US-9,564,914 Systems and methods for monitoring and compensation of analog to digital converter reference voltages
The present disclosure provides systems and methods for identifying changes in and failures of a reference voltage of an analog to digital (A/D) converter. A...
US-9,564,913 Synchronization of outputs from multiple digital-to-analog converters
Disclosed systems include a clock-multiplying phase locked loop (PLL) generating a clock signal for a DAC comprising a plurality of DAC cells, the systems...
US-9,564,912 Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator
Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a...
US-9,564,911 Integrated circuit having a multiplying injection-locked oscillator
Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or...
US-9,564,910 Clock generation circuit and method thereof
This invention discloses a clock generation circuit and a clock generation method for generating a clock. The clock generation circuit includes a reference...
US-9,564,909 Method and circuit for delay adjustment monotonicity in a delay line
A delay circuit device configured for delay adjustment monotonicity and method of operating therefor. This delay circuit device is configured with hybrid...
US-9,564,908 Digital phase-locked loop and method of operating the same
Provided are a digital phase-locked loop (DPLL) having improved signal characteristics, and a method of operating the DPLL. The DPLL includes a first tracking...
US-9,564,907 Multi-channel delay locked loop
A multi-channel delay locked loop includes a global delay locked loop and a plurality of local delay locked loops. The global delay locked loop is configured to...
US-9,564,906 Capacitance phase interpolation circuit and method thereof, and multi-phase generator applying the same
A capacitance phase interpolation circuit including a first capacitance phase interpolation unit and a second capacitance phase interpolation unit is disclosed....
US-9,564,905 Methods and systems for clocking a physical layer interface
A method for clocking a physical layer ("PHY") and a controller of a computing device, comprises the steps of: generating a reference clock signal;...
US-9,564,904 Asynchronous high-speed programmable divider
A method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal...
US-9,564,903 Port spreading
A semiconductor die having: a logic unit having a plurality of inputs/outputs; a plurality of pads whereby electrical connections can be made to the die; and a...
US-9,564,902 Dynamically configurable and re-configurable data path
An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the...
US-9,564,901 Self-timed dynamic level shifter with falling edge generator
A clock circuit configured to generate a falling edge independently of an input clock signal is disclosed. In one embodiment, a clock circuit includes an input...
US-9,564,900 Supply boost device
A device is disclosed that includes a driver circuit and a control circuit. The driver circuit is configured to provide an output signal according to an input...
US-9,564,899 Signal input circuit and operating method thereof
An input circuit includes: an input buffering unit suitable for receiving one or more input data, wherein each toggling time is defined according to a value of...
US-9,564,898 Power switch ramp rate control using selectable daisy-chained connection of enable to power switches or...
In an embodiment, an integrated circuit may include one or more power gated blocks and a power manager circuit. The power manager circuit may be configured to...
US-9,564,897 Apparatus for low power high speed integrated clock gating cell
An apparatus for an integrated clock gating cell is provided. The apparatus includes a logic gate that receives an unbuffered enable signal (E), a scan test...
US-9,564,896 Post-silicon tuning in voltage control of semiconductor integrated circuits
A circuit is disclosed that includes a plurality of voltage control circuits and a control module. Each of the voltage control circuits is controlled by a...
US-9,564,895 Touch key assembly and display device including the touch key assembly
A touch key assembly includes a light guiding film between a window and a display panel, a flexible printed circuit (FPC) film attached to the light guiding...
US-9,564,894 Capacitive input device interference detection and operation
A processing system for a capacitive input device comprises sensor circuitry and control logic. The sensor circuitry is configured to be communicatively coupled...
US-9,564,893 Touch switch and control panel
A technique reduces erroneous judgment due to effects of noise accompanying PWM control while using PWM control for brightness adjustment of light-emitting...
US-9,564,892 Apparatus and methods for radio frequency PIN diode switches
Apparatus and methods for radio frequency (RF) PIN diode switches are provided herein. In certain configurations, one or more PIN diode switches are integrated...
US-9,564,891 Low conducted emission solid state switch
A solid state switch may include a plurality of inputs, such as to receive a control signal to cause the solid state relay to selectively deliver power from an...
US-9,564,890 System-on-chip with dc-dc converters
A System-on-Chip includes a controller for generating a switching signal for driving a switching element of a power stage of a switched power converter. The...
US-9,564,889 Gate driving circuit and display device having the same
A gate driving circuit includes plural-stage output circuits, an Nth stage output circuit of the plural-stage output circuits includes an Nth stage shift...
US-9,564,888 Voltage generation apparatus
A voltage generation apparatus may include an external voltage sensing circuit configured to generate a first start signal and a second start signal by sensing...
US-9,564,887 High frequency absorptive switch architecture
An absorptive switch architecture suitable for use in high frequency RF applications. A switching circuit includes a common terminal and one or more ports, any...
US-9,564,886 Circuit and method for controlling operation voltage, and storage device
A circuit and a method for controlling operation voltage, and a storage device are provided. The circuit includes: a voltage boost unit adapted for: if...
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